Electrically erasable programmable read only memory device with an improved memory cell pattern layout

Claim 2

A semiconductor memory device comprising: a plurality of electrically rewritable memory cells connected in series to form NAND cells, each of said memory cells including a drain and a source; one or more source lines coupled to the sources of said memory cells through a contact hole; and bit lines arranged so as to avoid the contact hole, wherein said one or more source lines are arranged above said bit lines; wherein said bit lines are formed of a first conductive layer and said one or more source lines are formed of a second conductive layer; one or more isolated pattern portions to which said sources are connected and in which said bit lines of the first conductive layer are not formed, wherein said one or more isolated pattern portions are connected to said one or more source lines.

Claim 3

A semiconductor memory device according to claim 1, wherein said first conductive layer contains one of a polycide wire layer and a silicide wire layer.

Claim 4

A semiconductor memory device according to claim 1, wherein said second conductive layer contains a metal wire layer.

Claim 5

A semiconductor memory device according to claim 1, wherein each of said memory cells has a floating gate and a control gate, and has an FETMOS structure which is written or erased by discharging or injecting electrons to or from said floating gate.

Claim 6

A semiconductor memory device according to claim 4, wherein the discharging or injection of electrons to or from said floating gate is performed by a tunnel current.

Claim 7

A semiconductor memory device according to claim 3, wherein said first conductive layer contains one of a polycide wire layer and a silicide wire layer.

Claim 8

A semiconductor memory device comprising: a plurality of electrically rewritable memory cells allocated in arrays, each of which contains a drain and a source; one or more bit lines, which form a first conductive layer, connected to the drains of said memory cells and composed of one of a polycide wire layer and a silicide wire layer; and one or more source lines, which form a second conductive layer, connected to the sources of said memory cells and composed of metal wires, wherein said one or more source lines are arranged above said one or more bit lines; and an isolated pattern portion to which said sources are connected and in which said one or more bit lines of the first conductivity layer are not formed, wherein said isolated pattern portion is connected to said one or more source lines; wherein each of said memory cells has a floating gate and a control gate, and has an FETMOS structure which is written or erased by discharging or injecting electrons to or from said floating gate; wherein said floating gate and said control gate respectively include a third conductive layer and a fourth conductive layer, each layer composed of a semiconductor layer; wherein said memory cells are connected in series to form a NAND cell and one end of said NAND cell is coupled to said one or more bit lines and another end thereof is coupled to said one or more source lines.

Claim 9

A semiconductor memory device comprising: a plurality of electrically rewritable memory cells allocated in arrays, each of which contains a drain and a source; one or more bit lines, which form a first conductive layer, connected to the drains of said memory cells and composed of one of a polycide wire layer and a silicide wire layer; and one or more source lines, which form a second conductive layer, connected to the sources of said memory cells and composed of metal wires, wherein said one or more source lines are arranged above said one or more bit lines; and an isolated pattern portion to which said sources are connected and in which said one or more bit lines of the first conductivity layer are not formed, wherein said isolated pattern portion is connected to said one or more source lines; wherein each of said memory cells has a floating gate and a control gate, and has an FETMOS structure which is written or erased by discharging or injecting electrons to or from said floating gate; wherein said floating gate and said control gate respectively include a third conductive layer and a fourth conductive layer, each layer composed of a semiconductor layer; wherein said memory cells are connected in series to form a NAND cell and one end of said NAND cell is coupled to said one or more bit lines and another end thereof is coupled to said one or more source lines.

Claim 10

A semiconductor memory device according to claim 7, wherein the discharging or injection of electrons to or from said floating gate is performed by a tunnel current.

Claim 11

A semiconductor memory device comprising: a plurality of memory cell units, each of said memory cell units having memory cell transistors connected in series, each of said memory cell transistors having a charge storage layer, a control gate, a drain and a source; one or more bit lines connected to said drains at one end of one of said memory cell units and formed of a first conductive layer selected from one of silicide and polycide wires placed perpendicularly to the direction in which said memory cell units are arranged; one or more source lines connected to said sources at another end of one of said memory cell units and formed of a second conductive layer containing metal wires placed in parallel to the direction in which said memory cell units are arranged, wherein said one or more source lines are arranged above said one or more bit lines; and an isolated pattern which is selectively formed on said sources and couples to one of said one or more source lines, wherein said one or more bit lines are placed so as to avoid said isolated pattern.

Claim 12

A semiconductor memory device comprising: a plurality of memory cell units, each of said memory cell units having memory cell transistors connected in series, each of said memory cell transistors having a charge storage layer, a control gate, a drain and a source; one or more bit lines connected to said drains at one end of one of said memory cell units and formed of a first conductive layer selected from one of silicide and polycide wires placed perpendicularly to the direction in which said memory cell units are arranged; one or more source lines connected to said sources at another end of one of said memory cell units and formed of a second conductive layer containing metal wires placed in parallel to the direction in which said memory cell units are arranged, wherein said one or more source lines are arranged above said one or more bit lines; and an isolated pattern which is selectively formed on said sources and couples to one of said one or more source lines, wherein said one or more bit lines are placed so as to avoid said isolated pattern.

Claim 13

A semiconductor memory device according to claim 9, wherein said one or more bit lines are formed of a tungsten polycide layer with a thickness of 200 to 400 nm.

Claim 14

A semiconductor memory device according to claim 10, wherein said one or more source lines are formed by bringing said sources into direct contact with said tungsten polycide layer and then said tungsten polycide layer into contact with an Al layer such that said one or more source lines are not in contact with said one or more bit lines.

Claim 15

A semiconductor memory device according to claim 9, wherein said one or more bit lines are patterned by bending said one or more bit lines one after another, starting with the closest bit line to said isolated pattern, and making the amount of bend in said one or more bit lines less one after another as the distance from said isolated pattern increases.

Claim 16

A semiconductor memory device according to claim 12, wherein said one or more bit lines are formed of a tungsten polycide layer with a thickness of 200 to 400 nm.

Claim 17

A semiconductor memory device according to claim 13, wherein said one or more source lines are formed by bringing said sources into direct contact with said tungsten polycide layer and said tungsten polycide layer into contact with an Al layer such that said one or more source lines are not in contact with said one or more bit lines.

Claim 18

A semiconductor memory device as set forth in claim 9, wherein the quantum mechanical tunnelling effect is used to write data to said memory cells.

Claim 19

A semiconductor memory device as set forth in claim 1, wherein said bit lines constitute a single layer.

Claim 20

A semiconductor device according to claim 1, wherein said bit lines comprise bends shaped to avoid said contact hole, and an amount of bend in each bit line is progressively less as the distance from the contact hole increases.

Claim 21

A semiconductor device according to claim 7, wherein said bit lines comprise bends shaped to avoid said isolated pattern and an amount of bend in each bit line is progressively less as the distance from the isolated pattern increases.