US5596530A
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US
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Flash EPROM with block erase flags for over-erase protection
Assignee: Macronix International Co Ltd
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Filing: 1995-02-02
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Granted: 1997-01-21
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Expires: 2015-02-02
Abstract
Abstract A FLASH EPROM device includes a memory array organized into a plurality of blocks of memory cells. An energizing circuit applies energizing voltages to the blocks of memory cells to read and program addressed cells, and to erase selected blocks or the whole memory array. An erase verify circuit separately verifies erasure of blocks in the plurality of block memory cells. Control logic controls the energizing circuit to re-erase blocks which fail erase verify. The control logic includes a plurality of block erase flags which correspond to respective blocks of memory cells in the array. The erase verify is responsive to the block erase flags to verify only those blocks having a set block erase flag. If the block passes erase verify, then the block erase flag is reset. Only those blocks having a set block erase flag after the erase verify operation are re-erased. To support this operation, the circuit also includes the capability of erasing only a block of the memory array at a time.
Inventors
- 👤 Tien-Ler Lin
- 👤 Ray L. Wan
- 👤 Ling-Wen Hsiao
- 👤 Gilbert Sung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 11:00
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/344; G11C16/3445; G11C16/10; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 53
Claim 1
Independent Claim
111 words
An apparatus for storing data, comprising: a memory array, the memory array including a plurality of blocks of FLASH EPROM memory cells; energizing power supply circuits, coupled with the memory array, to apply energizing voltages to the plurality of blocks of memory cells to read and program addressed memory cells in the memory array and to erase the memory array; erase verify logic, coupled with the memory array, to separately verify erasure of blocks in the plurality of blocks of memory cells; and control circuits, coupled to the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits to re-erase blocks which fail erase verify.
Claim 2
Independent Claim
111 words
An apparatus for storing data, comprising: a memory array, the memory array including a plurality of blocks of FLASH EPROM memory cells; energizing power supply circuits, coupled with the memory array, to apply energizing voltages to the plurality of blocks of memory cells to read and program addressed memory cells in the memory array and to erase the memory array; erase verify logic, coupled with the memory array, to separately verify erasure of blocks in the plurality of blocks of memory cells; and control circuits, coupled to the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits to re-erase blocks which fail erase verify.
Claim 3
Dependent Claim
50 words
The apparatus of claim 1, wherein the control circuits include a plurality of block erase flags corresponding to respective blocks in the plurality of blocks of memory cells, and wherein the erase verify logic includes logic to control the plurality of block erase flags to indicate blocks to be re-erased.
Claim 4
Dependent Claim
85 words
The apparatus of claim 1, wherein: the plurality of blocks of memory cells include floating gate transistors having control gates, drains, and sources and block select circuits to selectively control application of the energizing voltages; and the energizing power supply circuits, coupled to the control gates, the drains, and the sources of the floating gate transistors and the block select circuits, apply a bias from at least one of the source and drain to the control gate of a floating gate transistor to be erased.
Claim 5
Dependent Claim
54 words
The apparatus of claim 3, wherein the block select circuits each include a pass gate, coupled to the sources of the floating gate transistors of the plurality of blocks of memory cells, which controls coupling of the energizing power supply circuits to the floating gate transistors of the plurality of blocks of memory cells.
Claim 6
Dependent Claim
29 words
The apparatus of claim 1, wherein the memory array, the energizing power supply circuits, the erase verify logic, and the control circuits are included on a single integrated circuit.
Claim 7
Dependent Claim
76 words
The apparatus of claim 3, wherein the floating gate transistor further comprises a floating gate, and a memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to the source to alter the threshold voltage level of the memory cell.
Claim 8
Dependent Claim
90 words
The apparatus of claim 3, wherein the floating gate transistor further comprises a floating gate, and a memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to a channel, the channel located between the drain and the source of the floating gate transistor, to alter the threshold voltage level of the memory cell.
Claim 9
Dependent Claim
82 words
The apparatus of claim 3, wherein the floating gate transistor further comprises a floating gate, and a memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a positive voltage to a channel, the channel located between the drain and the source of the floating gate transistor, to alter the threshold voltage level of the memory cell.
Claim 10
Independent Claim
138 words
An apparatus for storing data, comprising: a memory array, the memory array including a plurality of blocks of FLASH EPROM memory cells; energizing power supply circuits, coupled with the memory array, to apply energizing voltages to the plurality of blocks of memory cells to read and program addressed memory cells in the memory array and to erase selected blocks in the memory array; erase verify logic, coupled with the memory array, to separately verify erasure of the selected blocks in the plurality of blocks of memory cells; and control circuits, having a control input to receive erase commands indicating the selected blocks to be erased and coupled to the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits to erase the selected blocks and to re-erase blocks which fail erase verify.
Claim 11
Independent Claim
138 words
An apparatus for storing data, comprising: a memory array, the memory array including a plurality of blocks of FLASH EPROM memory cells; energizing power supply circuits, coupled with the memory array, to apply energizing voltages to the plurality of blocks of memory cells to read and program addressed memory cells in the memory array and to erase selected blocks in the memory array; erase verify logic, coupled with the memory array, to separately verify erasure of the selected blocks in the plurality of blocks of memory cells; and control circuits, having a control input to receive erase commands indicating the selected blocks to be erased and coupled to the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits to erase the selected blocks and to re-erase blocks which fail erase verify.
Claim 12
Dependent Claim
63 words
The apparatus of claim 9, wherein the control circuits include a plurality of block erase flags corresponding to respective blocks in the plurality of blocks of memory cells and logic responsive to the control input to set block erase flags for the selected blocks, and wherein the erase verify logic includes logic to reset block erase flags for blocks which pass erase verify.
Claim 13
Dependent Claim
49 words
The apparatus of claim 9 further comprises block select circuits, coupled with the control circuits, the plurality of blocks of memory cells, and the energizing power supply circuits, including a pass gate which connects the selected blocks to, and isolates blocks not selected from, the energizing power supply circuits.
Claim 14
Dependent Claim
55 words
The apparatus of claim 11, wherein: each memory cell within the plurality of blocks of memory cells includes a control gate, a drain and a source; and the pass gate of the block select circuits is coupled to the sources of the memory cells to control application of the energizing voltages to the memory cells.
Claim 15
Dependent Claim
68 words
The apparatus of claim 9, wherein: the plurality of blocks of memory cells includes floating gate transistors having control gates, drains, and sources; and the energizing power supply circuits, coupled to the control gates, the drains, and the sources of the floating gate transistors, apply a bias from at least one of the source and drain to the control gate of a floating gate transistor to be erased.
Claim 16
Dependent Claim
29 words
The apparatus of claim 9, wherein the memory array, the energizing power supply circuits, the erase verify logic, and the control circuits are integrated on a single integrated circuit.
Claim 17
Dependent Claim
76 words
The apparatus of claim 13, wherein the floating gate transistor further comprises a floating gate, and a memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to the source to alter the threshold voltage level of the memory cell.
Claim 18
Dependent Claim
90 words
The apparatus of claim 13, wherein the floating gate transistor further comprises a floating gate, and a memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to a channel, the channel located between the drain and the source of the floating gate transistor, to alter the threshold voltage level of the memory cell.
Claim 19
Dependent Claim
82 words
The apparatus of claim 13, wherein the floating gate transistor further comprises a floating gate, and a memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a positive voltage to a channel, the channel located between the drain and the source of the floating gate transistor, to alter the threshold voltage level of the memory cell.
Claim 20
Independent Claim
138 words
An apparatus for storing data, comprising: a memory array, the memory array including a plurality of blocks of floating gate memory cells; energizing power supply circuits, coupled with the memory array, to apply energizing voltages to the plurality of blocks of memory cells to read and program addressed memory cells in the memory array and to erase selected blocks in the memory array; erase verify logic, coupled with the memory array, to separately verify erasure of the selected blocks in the plurality of blocks of memory cells; and control circuits, having a control input to receive erase commands indicating the selected blocks to be erased and coupled to the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits to erase the selected blocks and to re-erase blocks which fail erase verify.
Claim 21
Independent Claim
138 words
An apparatus for storing data, comprising: a memory array, the memory array including a plurality of blocks of floating gate memory cells; energizing power supply circuits, coupled with the memory array, to apply energizing voltages to the plurality of blocks of memory cells to read and program addressed memory cells in the memory array and to erase selected blocks in the memory array; erase verify logic, coupled with the memory array, to separately verify erasure of the selected blocks in the plurality of blocks of memory cells; and control circuits, having a control input to receive erase commands indicating the selected blocks to be erased and coupled to the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits to erase the selected blocks and to re-erase blocks which fail erase verify.
Claim 22
Dependent Claim
63 words
The apparatus of claim 18, wherein the control circuits include a plurality of block erase flags corresponding to respective blocks in the plurality of blocks of memory cells and logic responsive to the control input to set block erase flags for the selected blocks, and wherein the erase verify logic includes logic to reset block erase flags for blocks which pass erase verify.
Claim 23
Dependent Claim
51 words
The apparatus of claim 18, further comprises block select circuits, coupled with the control circuits, the plurality of blocks of floating gate memory cells, and the energizing power supply circuits, including a pass gate which connects the selected blocks to, and isolates blocks not selected from, the energizing power supply circuits.
Claim 24
Dependent Claim
63 words
The apparatus of claim 20, wherein: each floating gate memory cell within the plurality of blocks of floating gate memory cells include a control gate, a drain and a source; and the pass gate of the block select circuits is coupled to the sources of the floating gate memory cells to control application of the energizing voltages to the floating gate memory cells.
Claim 25
Dependent Claim
68 words
The apparatus of claim 18, wherein: the plurality of blocks of floating gate memory cells include control gates, drains, and sources; and the energizing power supply circuits, coupled to the control gates, the drains, and the sources of the floating gate memory cells, apply a bias from at least one of the source and drain to the control gate of a floating gate memory cell to be erased.
Claim 26
Dependent Claim
29 words
The apparatus of claim 18, wherein the memory array, the energizing power supply circuits, the erase verify logic, and the control circuits are included on a single integrated circuit.
Claim 27
Dependent Claim
77 words
The apparatus of claim 22, wherein the floating gate memory cell further includes a floating gate, and the memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to the source to alter the threshold voltage level of the memory cell.
Claim 28
Dependent Claim
92 words
The apparatus of claim 22, wherein the floating gate memory cell further includes a floating gate, and the memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to a channel, the channel located between the drain and the source of the floating gate memory cell, to alter the threshold voltage level of the memory cell.
Claim 29
Dependent Claim
164 words
A FLASH EPROM integrated circuit, comprising: a memory array, the memory array including a plurality of blocks of FLASH EPROM memory cells; a plurality of block erase flags corresponding to respective blocks in the plurality of blocks of memory cells; command logic, coupled to command inputs, to set block erase flags corresponding to blocks to be erased; energizing power supply circuits, coupled with the memory array, to apply energizing voltages to read and program addressed memory cells in the memory array and to erase selected blocks in the memory array; erase verify logic, coupled with the memory array, for separately verifying erasure of the selected blocks in the plurality of blocks of memory cells and resetting block erase flags of blocks which pass erase verify; and control circuits, coupled to the plurality of block erase flags, the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits to erase the selected blocks having the set block erase flags.
Claim 30
Dependent Claim
164 words
A FLASH EPROM integrated circuit, comprising: a memory array, the memory array including a plurality of blocks of FLASH EPROM memory cells; a plurality of block erase flags corresponding to respective blocks in the plurality of blocks of memory cells; command logic, coupled to command inputs, to set block erase flags corresponding to blocks to be erased; energizing power supply circuits, coupled with the memory array, to apply energizing voltages to read and program addressed memory cells in the memory array and to erase selected blocks in the memory array; erase verify logic, coupled with the memory array, for separately verifying erasure of the selected blocks in the plurality of blocks of memory cells and resetting block erase flags of blocks which pass erase verify; and control circuits, coupled to the plurality of block erase flags, the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits to erase the selected blocks having the set block erase flags.
Claim 31
Dependent Claim
53 words
The integrated circuit of claim 26 further comprises block select circuits, coupled with the control circuits, the plurality of blocks of memory cells, and the energizing power supply circuits, including a pass gate which connects blocks to be erased to, and isolates blocks not to be erased from, the energizing power supply circuits.
Claim 32
Dependent Claim
56 words
The integrated circuit of claim 27, wherein: each memory cell within the plurality of blocks of memory cells include a control gate, a drain and a source; and the pass gate of the block select circuits is coupled to the sources of the memory cells to control application of the energizing voltages to the memory cells.
Claim 33
Dependent Claim
69 words
The integrated circuit of claim 26, wherein: the plurality of blocks of memory cells include floating gate transistors having control gates, drains, and sources; and the energizing power supply circuits, coupled to the control gates, the drains, and the sources of the floating gate transistors, apply a bias from at least one of the source and drain to the control gate of a floating gate transistor to be erased.
Claim 34
Dependent Claim
39 words
The integrated circuit of claim 26, wherein the memory array, the plurality of block erase flags, the command logic, the energizing power supply circuits, the erase verify logic, and the control circuits are integrated on a single integrated circuit.
Claim 35
Dependent Claim
83 words
The integrated circuit of claim 26, wherein a memory cell further comprises a control gate, a source, a drain, and a floating gate, the memory cell having a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to the source to alter the threshold voltage level of the memory cell.
Claim 36
Dependent Claim
97 words
The integrated circuit of claim 26, wherein a memory cell further comprises a control gate, a source, a drain, and a floating gate, and the memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to a channel, the channel located between the drain and the source of the memory cell, to alter the threshold voltage level of the memory cell.
Claim 37
Dependent Claim
77 words
The integrated circuit of claim 29, wherein the floating gate transistor further comprises a floating gate, and a memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to the source to alter the threshold voltage level of the memory cell.
Claim 38
Dependent Claim
91 words
The integrated circuit of claim 29, wherein the floating gate transistor further comprises a floating gate, and a memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to a channel, the channel located between the drain and the source of the floating gate transistor, to alter the threshold voltage level of the memory cell.
Claim 39
Independent Claim
153 words
An apparatus for storing data, comprising: a memory array, the memory array including a plurality of blocks of FLASH EPROM memory cells; block erase flags, coupled with the memory array, corresponding to respective blocks in the plurality of blocks of memory cells to select blocks of memory cells in the memory array for erasure; energizing power supply circuits, coupled with the memory array, to apply energizing voltages to the plurality of blocks of memory cells to erase selected blocks of memory cells; erase verify logic, coupled with the memory array, to separately verify the erasure of the selected blocks of memory cells and reset the block erase flags of the selected blocks of memory cells which pass erase verify; and control circuits, coupled to the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits to re-erase the selected blocks of memory cells which fail erase verify.
Claim 40
Independent Claim
153 words
An apparatus for storing data, comprising: a memory array, the memory array including a plurality of blocks of FLASH EPROM memory cells; block erase flags, coupled with the memory array, corresponding to respective blocks in the plurality of blocks of memory cells to select blocks of memory cells in the memory array for erasure; energizing power supply circuits, coupled with the memory array, to apply energizing voltages to the plurality of blocks of memory cells to erase selected blocks of memory cells; erase verify logic, coupled with the memory array, to separately verify the erasure of the selected blocks of memory cells and reset the block erase flags of the selected blocks of memory cells which pass erase verify; and control circuits, coupled to the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits to re-erase the selected blocks of memory cells which fail erase verify.
Claim 41
Dependent Claim
93 words
The apparatus of claim 35, wherein each memory cell within the plurality of memory cells comprises a floating gate transistor with a control gate, a floating gate, a drain, and a source, wherein the memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to the source to alter the threshold voltage level of the memory cell.
Claim 42
Dependent Claim
107 words
The apparatus of claim 35, wherein each memory cell within the plurality of memory cells comprises a floating gate transistor with a control gate, a floating gate, a drain, and a source, wherein the memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to a channel, the channel located between the drain and the source of the floating gate transistor, to alter the threshold voltage level of the memory cell.
Claim 43
Independent Claim
159 words
An apparatus for storing data, comprising: a memory array, the memory array including a plurality of blocks of FLASH EPROM memory cells; energizing power supply circuits, coupled with the memory array, to apply energizing voltages to the plurality of blocks of memory cells to read and program addressed cells in the memory array and to erase the memory array; block select circuits, coupled with the plurality of blocks of memory cells, and the energizing power supply circuits, including a pass gate which connects blocks to be erased to, and isolates blocks not to be erased from, the energizing power supply circuits; erase verify logic, coupled with the memory array, to separately verify the erasure of selected blocks in the plurality of blocks of memory cells; and control circuits, coupled to the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits to re-erase the selected blocks of memory cells which fail erase verify.
Claim 44
Independent Claim
159 words
An apparatus for storing data, comprising: a memory array, the memory array including a plurality of blocks of FLASH EPROM memory cells; energizing power supply circuits, coupled with the memory array, to apply energizing voltages to the plurality of blocks of memory cells to read and program addressed cells in the memory array and to erase the memory array; block select circuits, coupled with the plurality of blocks of memory cells, and the energizing power supply circuits, including a pass gate which connects blocks to be erased to, and isolates blocks not to be erased from, the energizing power supply circuits; erase verify logic, coupled with the memory array, to separately verify the erasure of selected blocks in the plurality of blocks of memory cells; and control circuits, coupled to the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits to re-erase the selected blocks of memory cells which fail erase verify.
Claim 45
Dependent Claim
55 words
The apparatus of claim 38, wherein: each memory cell within the plurality of blocks of memory cells include a control gate, a drain and a source; and the pass gate of the block select circuits is coupled to the sources of the memory cells to control application of the energizing voltages to the memory cells.
Claim 46
Dependent Claim
75 words
The apparatus of claim 39, wherein the memory cell further includes a floating gate, and the memory cell has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to the source to alter the threshold voltage level of the memory cell.
Claim 47
Dependent Claim
85 words
The apparatus of claim 39, wherein the memory cell further includes a floating gate, and has a threshold voltage level which varies with an amount of charge in the floating gate and wherein the energizing voltages applied by the energizing power supply circuits during an erase operation comprise a non-positive voltage to the control gate and a positive voltage to a channel, the channel located between the drain and the source of the memory cell, to alter the threshold voltage level of the memory cell.
Claim 48
Independent Claim
108 words
A method of storing data comprising the steps of: providing a memory array having a plurality of blocks of FLASH EPROM memory cells; setting block erase flags corresponding to respective blocks in the plurality of blocks of memory cells for erasure; energizing the plurality of blocks of memory cells for erasure of blocks of memory cells indicated by the block erase flags; verifying the erasure of the blocks of memory cells indicated by the block erase flags; resetting the block erase flags after successful erase verify of corresponding blocks of memory cells; and re-energizing blocks of memory cells to re-erase blocks of memory cells which fail erase verify.
Claim 49
Independent Claim
108 words
A method of storing data comprising the steps of: providing a memory array having a plurality of blocks of FLASH EPROM memory cells; setting block erase flags corresponding to respective blocks in the plurality of blocks of memory cells for erasure; energizing the plurality of blocks of memory cells for erasure of blocks of memory cells indicated by the block erase flags; verifying the erasure of the blocks of memory cells indicated by the block erase flags; resetting the block erase flags after successful erase verify of corresponding blocks of memory cells; and re-energizing blocks of memory cells to re-erase blocks of memory cells which fail erase verify.
Claim 50
Dependent Claim
46 words
The method of claim 42, wherein the step of verifying the erasure of the blocks of memory cells further comprises the step of verifying each block of memory cells in sequence until each block of memory cells indicated by the block erase flags has been verified.
Claim 51
Dependent Claim
29 words
The method of claim 43 further comprises the step of verifying a next block of memory cells in the sequence upon detection of memory cells that fail erase verify.
Claim 52
Dependent Claim
37 words
The method of claim 43 wherein the step of verifying each block of memory cells in the sequence further comprises the step of sharing a set of sense amps between the plurality of blocks of memory cells.
Claim 53
Dependent Claim
65 words
The method of claim 42, wherein the step of energizing the plurality of blocks of memory cells for erasure comprises applying a non-positive voltage to a control gate of a memory cell and applying a positive voltage to a source of the memory cell to alter a threshold voltage level which varies with an amount of charge in a floating gate of the memory cell.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-21 | 2000-07-22 | 2001-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-21 | 2004-07-22 | 2005-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-21 | 2008-07-22 | 2009-01-21 | $7700.00 | Window Closed / Lapsed |