US5600847A
Expired / Lapsed
US
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Three input arithmetic logic unit with mask generator
Assignee: Texas Instruments Inc
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Filing: 1995-06-07
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Granted: 1997-02-04
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Expires: 2015-06-07
Abstract
Abstract A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2 N , with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235). The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
Inventors
- 👤 Karl M. Guttag
- 👤 Keith Balmer
- 👤 Robert J. Gove
- 👤 Christopher J. Read
- 👤 Jeremiah E. Golston
- 👤 Sydney W. Poland
- 👤 Nicholas Ing-Simmons
- 👤 Philip Moyse
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:07
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/57
Claims Analysis
Total Claims: 81
Claim 1
Independent Claim
237 words
A data processing apparatus comprising: an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input signal for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least one combination performing a logical OR of 1) a logical AND of a first arithmetic combination of said first multibit input plus said second multibit input with said third multibit input, and 2) a logical AND of a second arithmetic combination opposite to said first arithmetic combination of said first multibit input and said second multibit input with an inverse of said third multibit input; a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit; a second data source supplying a second multibit digital signal to said second data input of said arithmetic logic unit; a third data source supplying a third multibit digital signal; a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask corresponding to said third multibit digital signal.
Claim 2
Dependent Claim
237 words
A data processing apparatus comprising: an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input signal for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least one combination performing a logical OR of 1) a logical AND of a first arithmetic combination of said first multibit input plus said second multibit input with said third multibit input, and 2) a logical AND of a second arithmetic combination opposite to said first arithmetic combination of said first multibit input and said second multibit input with an inverse of said third multibit input; a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit; a second data source supplying a second multibit digital signal to said second data input of said arithmetic logic unit; a third data source supplying a third multibit digital signal; a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask corresponding to said third multibit digital signal.
Claim 3
Dependent Claim
178 words
The data processing apparatus of claim 1, wherein: said arithmetic logic unit further includes a control input receiving a function signal defining said combination of said first, second and third input signals; said data processing apparatus further comprising: a source of a stream of instruction words, said instruction words having a plurality of formats including at least one immediate instruction word format defining an immediate field; an instruction decoder connected to said source of said stream of instruction words, said arithmetic logic unit, said first data source, said second data source and said third data source, said instruction decoder receiving individual instruction words of said stream of instructions words, generating said function signal corresponding to each received individual instruction word, supplying said function signal to said control input of said arithmetic logic unit, and controlling said first, second and third data sources corresponding to each received individual instruction word, including controlling said third data source to supply said third multibit digital signal equal to said immediate field upon receiving an instruction word in said immediate field instruction format.
Claim 4
Dependent Claim
62 words
The data processing apparatus of claim 1, further comprising: a first input multiplexer having a first input connected to said first data source, a second input connected to said third data source and an output supplying a selected one of either said first multibit digital signal or said third multibit digital signal to said first data input of said arithmetic logic unit.
Claim 5
Dependent Claim
189 words
The data processing apparatus of claim 1, further comprising: a data register file including a plurality of data registers for storing data, a first output bus connected to said first data input of said arithmetic logic unit for recalling from a first specified data register data stored therein, thereby forming said first data source, a second output bus connected to said second data input of said arithmetic logic unit for recalling from a second specified data register data stored therein, thereby forming said second data source, a third output bus connected to said data input of said mask generator for recalling from a third specified data register data stored therein, thereby forming said third source, a first input bus connected to said output of said arithmetic logic unit for storing in a fourth specified one of said data registers said combination of said first, second and third input signals, and a predetermined one of said plurality of data registers being a special function data register storing therein a default mask amount; and said input of said mask generator receives said default mask amount of said special function data register.
Claim 6
Dependent Claim
59 words
The data processing apparatus of claim 4, further comprising: a mask input multiplexer having a first input connected to said third data source, a second input connected to said special function data register and an output supplying a selected one of either said third multibit digital signal or said default mask amount to said input of said mask generator.
Claim 7
Dependent Claim
40 words
The data processing apparatus of claim 1, wherein: said mask generator supplies to said third data input of said arithmetic logic unit said multibit digital mask having a number of right justified "1's" corresponding to said third multibit digital signal.
Claim 8
Dependent Claim
101 words
The data processing apparatus of claim 6, further comprising: a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said mask generator connected to said instruction decoder for modifying said multibit digital mask to have all "1's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 9
Dependent Claim
128 words
The data processing apparatus of claim 6, further comprising: a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said instruction decoder modifying said function signals supplied to said arithmetic logic unit upon receipt of a mask modification instruction whereby said arithmetic logic unit forms said mixed arithmetic and Boolean combination as if said mask generator formed said multibit digital mask having all "1's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 10
Dependent Claim
40 words
The data processing apparatus of claim 1, wherein: said mask generator supplies to said third data input of said arithmetic logic unit said multibit digital mask having a number of right justified "0's" corresponding to said third multibit digital signal.
Claim 11
Dependent Claim
101 words
The data processing apparatus of claim 9, further comprising: a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said mask generator connected to said instruction decoder for modifying said multibit digital mask to have all "0's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 12
Dependent Claim
128 words
The data processing apparatus of claim 9, further comprising: a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said instruction decoder modifying said function signals supplied to said arithmetic logic unit upon receipt of a mask modification instruction whereby said arithmetic logic unit forms said mixed arithmetic and Boolean combination as if said mask generator formed said multibit digital mask having all "0's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 13
Dependent Claim
40 words
The data processing apparatus of claim 1, wherein: said mask generator supplies to said third data input of said arithmetic logic unit said multibit digital mask having a number of left justified "1's" corresponding to said third multibit digital signal.
Claim 14
Dependent Claim
101 words
The data processing apparatus of claim 12, further comprising: a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said mask generator connected to said instruction decoder for modifying said multibit digital mask to have all "1's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 15
Dependent Claim
128 words
The data processing apparatus of claim 12, further comprising: a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said instruction decoder modifying said function signals supplied to said arithmetic logic unit upon receipt of a mask modification instruction whereby said arithmetic logic unit forms said mixed arithmetic and Boolean combination as if said mask generator formed said multibit digital mask having all "1's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 16
Dependent Claim
40 words
The data processing apparatus of claim 1, wherein: said mask generator supplies to said third data input of said arithmetic logic unit said multibit digital mask having a number of left justified "0's" corresponding to said third multibit digital signal.
Claim 17
Dependent Claim
101 words
The data processing apparatus of claim 15, further comprising: a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said mask generator connected to said instruction decoder for modifying said multibit digital mask to have all "0's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 18
Dependent Claim
128 words
The data processing apparatus of claim 15, further comprising: a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said instruction decoder modifying said function signals supplied to said arithmetic logic unit upon receipt of a mask modification instruction whereby said arithmetic logic unit forms said mixed arithmetic and Boolean combination as if said mask generator formed said multibit digital mask having all "0's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 19
Dependent Claim
39 words
The data processing apparatus of claim 1, wherein: said mask generator supplies to said third data input of said arithmetic logic unit said multibit digital mask corresponding to a bit specific unary operation on said second multibit digital signal.
Claim 20
Dependent Claim
35 words
The data processing apparatus of claim 18, wherein: said bit specific unary operation of mask generator generates a number corresponding to the bit position of a left most "1" in said second multibit digital signal.
Claim 21
Dependent Claim
36 words
The data processing apparatus of claim 18, wherein: said bit specific unary operation of said mask generator generates a number corresponding to the bit position of a right most "1" in said second multibit digital signal.
Claim 22
Dependent Claim
49 words
The data processing apparatus of claim 18, wherein: said bit specific unary operation of said mask generator generates a number corresponding to the bit position of a left most bit in said second multibit digital signal which differs from a most significant bit of said second multibit digital signal.
Claim 23
Dependent Claim
49 words
The data processing apparatus of claim 18, wherein: said bit specific unary operation of said mask generator generates a number corresponding to the bit position of a right most bit in said second multibit digital signal which differs from a least significant bit of said second multibit digital number.
Claim 24
Dependent Claim
110 words
The data processing apparatus of claim 18, wherein: said bit specific unary operation of said mask generator generates a number corresponding to a selected one of either the bit position of a left most "1" in said second multibit digital signal, the bit position of a right most "1" in said second multibit digital signal, the bit position of a left most bit in said second multibit digital signal which differs from a most significant bit of said second multibit digital signal, or the bit position of a right most bit in said second multibit digital signal which differs from a least significant bit of said second multibit digital number.
Claim 25
Dependent Claim
26 words
The data processing apparatus of claim 1, wherein: said mask generator forms said multibit digital mask as a digital pattern repeated an integral number of times.
Claim 26
Dependent Claim
128 words
The data processing apparatus of claim 24, further comprising: a status register storing a size indicator indicating a number of sections selected from a plurality of possible number of sections; said arithmetic logic unit being connected to said status register and divided into a number of sections corresponding to said size indicator, each section generating at a corresponding output a digital resultant signal representing a combination of respective subsets of said first, second and third input signals; and said mask generator being connected to said status register and forming said multibit digital mask having said digital pattern repeated a number of times equal to said number of sections of said size indicator, whereby each section of said arithmetic logic unit receives said digital pattern from said mask generator.
Claim 27
Dependent Claim
59 words
The data processing apparatus of claim 1, further comprising: a fourth data source supplying a fourth multibit digital signal; and said mask generator supplies to said third data input of said arithmetic logic unit said multibit digital mask corresponding to the replication of a selected number of bits of said fourth multibit digital signal a selected number of times.
Claim 28
Dependent Claim
61 words
The data processing apparatus of claim 26, wherein: said fourth data source includes a multiple flags register for storing therein said fourth multibit digital signal; and said data processing apparatus further comprises a status register connected to said mask generator for storing indications of said selected number of bits of said fourth multibit digital signal and said selected number of times.
Claim 29
Dependent Claim
90 words
The data processing apparatus of claim 1, further comprising: at least one additional mask generator, each additional mask generator generating a corresponding additional multibit digital mask; and a third input multiplexer having a first input connected to said mask generator and at least one additional input mask generator input, each additional mask generator input connected to a corresponding additional mask generator for supplying a selected one of either said first multibit digital mask or a corresponding additional multibit digital mask to said third data input of said arithmetic logic unit.
Claim 30
Dependent Claim
59 words
The data processing apparatus of claim 1, further comprising: a third input multiplexer having a first input connected to said mask generator and a second input receiving said third multibit digital signal, for supplying a selected one of either said multibit digital mask or said third multibit digital signal to said third data input of said arithmetic logic unit.
Claim 31
Dependent Claim
150 words
The data processing apparatus of claim 1, further comprising: a data register file including a plurality of data registers for storing data, a first output bus connected to said first data input of said arithmetic logic unit for recalling from a first specified data register data stored therein, thereby forming said first data source, a second output bus connected to said second data input of said arithmetic logic unit for recalling from a second specified data register data stored therein, thereby forming said second data source, a third output bus connected to said data input of said mask generator for recalling from a third specified data register data stored therein, thereby forming said third source, and a first input bus connected to said output of said arithmetic logic unit for storing in a fourth specified one of said data registers said combination of said first, second and third input signals.
Claim 32
Dependent Claim
106 words
The data processing apparatus of claim 1, wherein: said at least one combination performing a logical OR of 1) a logical AND of a first arithmetic combination of said first multibit input plus said second multibit input with said third multibit input, and 2) a logical AND of a second arithmetic combination opposite to said first arithmetic combination of said first multibit input and said second multibit input with an inverse of said third multibit input consists of ((A+B) AND C) OR ((A-B) AND NOT C), where A is said first multibit input, B is said second multibit input and C is said third multibit input.
Claim 33
Dependent Claim
106 words
The data processing apparatus of claim 1, wherein: said at least one combination performing a logical OR of 1) a logical AND of a first arithmetic combination of said first multibit input plus said second multibit input with said third multibit input, and 2) a logical AND of a second arithmetic combination opposite to said first arithmetic combination of said first multibit input and said second multibit input with an inverse of said third multibit input consists of ((A-B) AND C) OR ((A+B) AND NOT C), where A is said first multibit input, B is said second multibit input and C is said third multibit input.
Claim 34
Dependent Claim
282 words
A data processing system comprising: a data system bus transferring data and addresses; an system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus; a data processor circuit connected to said data system bus, said data processor circuit including an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input signal for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least one combination performing a logical OR of 1) a logical AND of a first arithmetic combination of said first multibit input plus said second multibit input with said third multibit input, and 2) a logical AND of a second arithmetic combination opposite to said first arithmetic combination of said first multibit input and said second multibit input with an inverse of said third multibit input; a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit, a second data source supplying a second multibit digital signal to said second data input of said arithmetic logic unit, a third data source supplying a third multibit digital signal, a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask corresponding to said third multibit digital signal.
Claim 35
Dependent Claim
282 words
A data processing system comprising: a data system bus transferring data and addresses; an system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus; a data processor circuit connected to said data system bus, said data processor circuit including an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input signal for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least one combination performing a logical OR of 1) a logical AND of a first arithmetic combination of said first multibit input plus said second multibit input with said third multibit input, and 2) a logical AND of a second arithmetic combination opposite to said first arithmetic combination of said first multibit input and said second multibit input with an inverse of said third multibit input; a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit, a second data source supplying a second multibit digital signal to said second data input of said arithmetic logic unit, a third data source supplying a third multibit digital signal, a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask corresponding to said third multibit digital signal.
Claim 36
Dependent Claim
183 words
The data processing system of claim 33, wherein: said data processor circuit wherein said arithmetic logic unit further includes a control input receiving a function signal defining said combination of said first, second and third input signals, said imaging processing apparatus further comprising: a source of a stream of instruction words, said instruction words having a plurality of formats including at least one immediate instruction word format defining an immediate field; an instruction decoder connected to said source of said stream of instruction words, said arithmetic logic unit, said first data source, said second data source and said third data source, said instruction decoder receiving individual instruction words of said stream of instructions words, generating said function signal corresponding to each received individual instruction word, supplying said function signal to said control input of said arithmetic logic unit, and controlling said first, second and third data sources corresponding to each received individual instruction word, including controlling said third data source to supply said third multibit digital signal equal to said immediate field upon receiving an instruction word in said immediate field instruction format.
Claim 37
Dependent Claim
67 words
The data processing system of claim 33, wherein: said data processor circuit further includes a first input multiplexer having a first input connected to said first data source, a second input connected to said third data source and an output supplying a selected one of either said first multibit digital signal or said third multibit digital signal to said first data input of said arithmetic logic unit.
Claim 38
Dependent Claim
194 words
The data processing system of claim 33, wherein: said data processor circuit further includes a data register file including a plurality of data registers for storing data, a first output bus connected to said first data input of said arithmetic logic unit for recalling from a first specified data register data stored therein, thereby forming said first data source, a second output bus connected to said second data input of said arithmetic logic unit for recalling from a second specified data register data stored therein, thereby forming said second data source, a third output bus connected to said data input of said mask generator for recalling from a third specified data register data stored therein, thereby forming said third source, a first input bus connected to said output of said arithmetic logic unit for storing in a fourth specified one of said data registers said combination of said first, second and third input signals, and a predetermined one of said plurality of data registers being a special function data register storing therein a default mask amount, and said input of said mask generator receives said default mask amount of said special function data register.
Claim 39
Dependent Claim
64 words
The data processing system of claim 36, wherein: said data processor circuit further includes a mask input multiplexer having a first input connected to said third data source, a second input connected to said special function data register and an output supplying a selected one of either said third multibit digital signal or said default mask amount to said input of said mask generator.
Claim 40
Dependent Claim
45 words
The data processing system of claim 33, wherein: said data processor circuit wherein said mask generator supplies to said third data input of said arithmetic logic unit said multibit digital mask having a number of right justified "1's" corresponding to said third multibit digital signal.
Claim 41
Dependent Claim
106 words
The data processing system of claim 38, wherein: said data processor circuit further including a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said mask generator connected to said instruction decoder for modifying said multibit digital mask to have all "1's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 42
Dependent Claim
120 words
The data processing system of claim 38, wherein: said data processor circuit further including a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said instruction decoder modifying said function signals supplied to said arithmetic logic unit upon receipt of a mask modification instruction whereby said arithmetic logic unit forms said mixed arithmetic and Boolean combination as if said mask generator formed said multibit digital mask having all "1's" for a zero input.
Claim 43
Dependent Claim
45 words
The data processing system of claim 33, wherein: said data processor circuit wherein said mask generator supplies to said third data input of said arithmetic logic unit said multibit digital mask having a number of right justified "0's" corresponding to said third multibit digital signal.
Claim 44
Dependent Claim
106 words
The data processing system of claim 41, wherein: said data processor circuit further including a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said mask generator connected to said instruction decoder for modifying said multibit digital mask to have all "0's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 45
Dependent Claim
133 words
The data processing system of claim 41, wherein: said data processor circuit further including a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said instruction decoder modifying said function signals supplied to said arithmetic logic unit upon receipt of a mask modification instruction whereby said arithmetic logic unit forms said mixed arithmetic and Boolean combination as if said mask generator formed said multibit digital mask having all "0's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 46
Dependent Claim
45 words
The data processing system of claim 33, wherein: said data processor circuit wherein said mask generator supplies to said third data input of said arithmetic logic unit said multibit digital mask having a number of left justified "1's" corresponding to said third multibit digital signal.
Claim 47
Dependent Claim
106 words
The data processing system of claim 44, wherein: said data processor circuit further includes a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said mask generator connected to said instruction decoder for modifying said multibit digital mask to have all "1's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 48
Dependent Claim
133 words
The data processing system of claim 44, wherein: said data processor circuit further including a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said instruction decoder modifying said function signals supplied to said arithmetic logic unit upon receipt of a mask modification instruction whereby said arithmetic logic unit forms said mixed arithmetic and Boolean combination as if said mask generator formed said multibit digital mask having all "1's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 49
Dependent Claim
45 words
The data processing system of claim 33, wherein: said data processor circuit wherein said mask generator supplies to said third data input of said arithmetic logic unit said multibit digital mask having a number of left justified "0's" corresponding to said third multibit digital signal.
Claim 50
Dependent Claim
106 words
The data processing system of claim 47, wherein: said data processor circuit further includes a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said mask generator connected to said instruction decoder for modifying said multibit digital mask to have all "0's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 51
Dependent Claim
133 words
The data processing system of claim 47, wherein: said data processor circuit further includes a source of instructions including at least one mask function modification instruction; an instruction decoder receiving instructions from said source of instructions and generating a set of function signals corresponding to each received instruction; said arithmetic logic unit connected to said instruction decoder and generating said mixed arithmetic and Boolean combination corresponding to said function signals; and said instruction decoder modifying said function signals supplied to said arithmetic logic unit upon receipt of a mask modification instruction whereby said arithmetic logic unit forms said mixed arithmetic and Boolean combination as if said mask generator formed said multibit digital mask having all "0's" for a zero input upon receipt of one of said at least one mask function modification instruction.
Claim 52
Dependent Claim
44 words
The data processing system of claim 33, wherein: said data processor circuit wherein said mask generator supplies to said third data input of said arithmetic logic unit said multibit digital mask corresponding to a bit specific unary operation on said second multibit digital signal.
Claim 53
Dependent Claim
40 words
The data processing system of claim 50, wherein: said data processor circuit wherein said bit specific unary operation of mask generator generates a number corresponding to the bit position of a left most "1" in said second multibit digital signal.
Claim 54
Dependent Claim
41 words
The data processing system of claim 50, wherein: said data processor circuit wherein said bit specific unary operation of said mask generator generates a number corresponding to the bit position of a right most "1" in said second multibit digital signal.
Claim 55
Dependent Claim
54 words
The data processing system of claim 50, wherein: said data processor circuit wherein said bit specific unary operation of said mask generator generates a number corresponding to the bit position of a left most bit in said second multibit digital signal which differs from a most significant bit of said second multibit digital signal.
Claim 56
Dependent Claim
54 words
The data processing system of claim 50, wherein: said data processor circuit wherein said bit specific unary operation of said mask generator generates a number corresponding to the bit position of a right most bit in said second multibit digital signal which differs from a least significant bit of said second multibit digital number.
Claim 57
Dependent Claim
115 words
The data processing system of claim 50, wherein: said data processor circuit wherein said bit specific unary operation of said mask generator generates a number corresponding to a selected one of either the bit position of a left most "1" in said second multibit digital signal, the bit position of a right most "1" in said second multibit digital signal, the bit position of a left most bit in said second multibit digital signal which differs from a most significant bit of said second multibit digital signal, or the bit position of a right most bit in said second multibit digital signal which differs from a least significant bit of said second multibit digital number.
Claim 58
Dependent Claim
31 words
The data processing system of claim 33, wherein: said data processor circuit wherein said mask generator forms said multibit digital mask as a digital pattern repeated an integral number of times.
Claim 59
Dependent Claim
133 words
The data processing system of claim 56, wherein: said data processor circuit further includes a status register storing a size indicator indicating a number of sections selected from a plurality of possible number of sections, said arithmetic logic unit being connected to said status register and divided into a number of sections corresponding to said size indicator, each section generating at a corresponding output a digital resultant signal representing a combination of respective subsets of said first, second and third input signals, and said mask generator being connected to said status register and forming said multibit digital mask having said digital pattern repeated a number of times equal to said number of sections of said size indicator, whereby each section of said arithmetic logic unit receives said digital pattern from said mask generator.
Claim 60
Dependent Claim
64 words
The data processing system of claim 33, wherein said data processor circuit further includes a fourth data source supplying a fourth multibit digital signal, and said mask generator supplies to said third data input of said arithmetic logic unit said multibit diqital mask corresponding to the replication of a selected number of bits of said fourth multibit digital signal a selected number of times.
Claim 61
Dependent Claim
66 words
The data processing system of claim 58, wherein: said data processor circuit wherein said fourth data source includes a multiple flags register for storing therein said fourth multibit digital signal, and said data processor circuit further includes a status register connected to said mask generator for storing indications of said selected number of bits of said fourth multibit digital signal and said selected number of times.
Claim 62
Dependent Claim
94 words
The data processing system of claim 33, wherein: said data processor circuit further includes at least one additional mask generator, each additional mask generator generating a corresponding additional multibit digital mask, and a third input multiplexer having a first input connected to said mask generator and at least one additional mask generator input, each additional mask generator input connected to a corresponding additional mask generator for supplying a selected one of either said first multibit digital mask or a corresponding additional multibit digital mask to said third data input of said arithmetic logic unit.
Claim 63
Dependent Claim
64 words
The data processing system of claim 33, wherein: said data processor circuit further includes a third input multiplexer having a first input connected to said mask generator and a second input receiving said third multibit digital signal, for supplying a selected one of either said multibit digital mask or said third multibit digital signal to said third data input of said arithmetic logic unit.
Claim 64
Dependent Claim
76 words
The data processing system of claim 33, wherein: said data processor circuit further includes a plurality of data memories connected to said data processor circuit, an instruction memory supplying instructions to said data processor circuit, and a transfer controller connected to said data system bus, each of said data memories and said instruction memory controlling data transfer between said system memory and said plurality of data memories and between said system memory and said instruction memory.
Claim 65
Dependent Claim
98 words
The data processing system of claim 62, wherein: said data processor circuit further includes at least one additional data processor circuit identical to said data processor circuit, a plurality of additional data memories connected to each additional data processor circuit, an additional instruction memory supplying instructions to each additional data processor circuit, and said transfer controller is further connected to each of said additional data memories and each said additional instruction memory controlling data transfer between said system memory and said each of said additional data memories and between said system memory and each said additional instruction memory.
Claim 66
Dependent Claim
51 words
The data processing system of claim 63, wherein: said data processor circuit including said data processor circuit, said data memories, said instruction memories, each of said additional data processor circuits, each of said additional data memories, each additional instruction memory and said transfer controller are formed on a single integrated circuit.
Claim 67
Dependent Claim
89 words
The data processing system of claim 62, wherein: said data processor circuit further includes a master data processor, a plurality of master data memories connected to said master data processor, at least one master instruction memory supplying instructions to said master data processor, and said transfer controller is further connected to each of said master data memories and each said master instruction memory controlling data transfer between said system memory and said each of said master data memories and between said system memory and each said master instruction memory.
Claim 68
Dependent Claim
48 words
The data processing system of claim 65, wherein: said data processor circuit including said data processor circuit, said data memories, said instruction memories, said master data processor, each of said master data memories, each master instruction memory and said transfer controller are formed on a single integrated circuit.
Claim 69
Dependent Claim
59 words
The data processing system of claim 33, wherein: said system memory consists of an image memory storing image data in a plurality of pixels; and said data processor system further comprising: an image display unit connected to said image memory generating a visually perceivable output of an image consisting of a plurality of pixels stored in said image memory.
Claim 70
Dependent Claim
64 words
The data processing system of claim 67, further comprising: a palette forming a connection between said image memory and said image display unit, said palette transforming pixels recalled from said image memory into video signals driving said image display unit; and wherein said data processor circuit further includes a frame controller connected to said palette controlling said palette transformation of pixels into video signals.
Claim 71
Dependent Claim
56 words
The data processing system of claim 33, wherein: said system memory consists of an image memory storing image data in a plurality of pixels; and said data processor system further comprising: a printer connected to said image memory generating a printed output of an image consisting of a plurality of pixels stored in said image memory.
Claim 72
Dependent Claim
15 words
The data processing system of claim 69, wherein: said printer consists of a color printer.
Claim 73
Dependent Claim
64 words
The data processing system of claim 69, further comprising: a printer controller forming a connection between said image memory and said printer, said printer controller transforming pixels recalled from said image memory into print signals driving said printer; and wherein said data processor circuit further includes a frame controller connected to said print controller controlling said print controller transformation of pixels into print signals.
Claim 74
Dependent Claim
44 words
The data processing system of claim 33, wherein: said system memory consists of an image memory storing image data in a plurality of pixels; and said data processor system further comprising: an imaging device connected to said image memory generating an image signal input.
Claim 75
Dependent Claim
70 words
The data processing system of claim 72, further comprising: an image capture controller forming a connection between said imaging device and said image memory, said image capture controller transforming said image signal into pixels supplied for storage in said image memory; and wherein said data processor circuit further includes a frame controller connected to said image capture controller controlling said image capture controller transformation of said image signal into pixels.
Claim 76
Dependent Claim
22 words
The data processing system of claim 33, further comprising: a modem connected to said data system bus and to a communications line.
Claim 77
Dependent Claim
19 words
The data processing system of claim 33, further comprising: a host processing system connected to said data system bus.
Claim 78
Dependent Claim
35 words
The data processing system of claim 75, further comprising: a host system bus connected to said host processing system transferring data and addresses; and at least one host peripheral connected to said host system bus.
Claim 79
Dependent Claim
155 words
The data processing system of claim 33, wherein: said data processor circuit further includes a data register file including a plurality of data registers for storing data, a first output bus connected to said first data input of said arithmetic logic unit for recalling from a first specified data register data stored therein, thereby forming said first data source, a second output bus connected to said second data input of said arithmetic logic unit for recalling from a second specified data register data stored therein, thereby forming said second data source, a third output bus connected to said data input of said mask generator for recalling from a third specified data register data stored therein, thereby forming said third source, and a first input bus connected to said output of said arithmetic logic unit for storing in a fourth specified one of said data registers said combination of said first, second and third input signals.
Claim 80
Dependent Claim
116 words
The data processing system of claim 33, wherein: said data processor circuit wherein said at least one combination of said arithmetic logic unit performing a logical OR of 1) a logical AND of a first arithmetic combination of said first multibit input plus said second multibit input with said third multibit input, and 2) a logical AND of a second arithmetic combination opposite to said first arithmetic combination of said first multibit input and said second multibit input with an inverse of said third multibit input consists of ((A+B) AND C) OR ((A-B) AND NOT C), where A is said first multibit input, B is said second multibit input and C is said third multibit input.
Claim 81
Dependent Claim
116 words
The data processing system of claim 33, wherein: said data processor circuit wherein said at least one combination of said arithmetic logic unit performing a logical OR of 1) a logical AND of a first arithmetic combination of said first multibit input plus said second multibit input with said third multibit input, and 2) a logical AND of a second arithmetic combination opposite to said first arithmetic combination of said first multibit input and said second multibit input with an inverse of said third multibit input consists of ((A-B) AND C) OR ((A+B) AND NOT C), where A is said first multibit input, B is said second multibit input and C is said third multibit input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |