US5602772A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1994-09-20
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Granted: 1997-02-11
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Expires: 2014-09-20
Abstract
Abstract A dynamic semiconductor memory device according to the present invention, comprises a plurality of first bit lines, a plurality of second bit lines which are partially laminated above the first bit lines and, together with the first bit lines, form bit-line pairs to build a folded bit-line structure, a plurality of word lines arranged so as to cross the first bit lines and the second bit lines, and at least one memory cell array in which a plurality of memory cells connected to the first bit lines and the second bit lines are arranged in a matrix, wherein the memory cell array includes a plurality of first areas in which a plurality of memory cells are arranged, and a plurality of second memory areas which are arranged so as to alternate with the first areas and contain no memory cell, and the second memory areas include areas where the first bit lines of the specified number of the bit-line pairs are connected to the second bit lines and the second bit lines are connected to the first bit lines.
Inventors
- 👤 Hiroaki Nakano
- 👤 Daisaburo Takashima
- 👤 Tohru Ozaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:34
CPC Classifications
H; H10; H10B; H10B12/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; H10B12/30; H10W; H10W20/00; H10W20/40; H10W20/495
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
160 words
A dynamic semiconductor memory device comprising: first bit line layer having a plurality of first bit lines; a second bit line layer, which is laminated above said first bit line layer via an insulating layer, having a plurality of second bit lines to form bit-line pairs together with said first bit lines, to build a folded bit-line structure; word lines arranged so as to cross said first bit lines and said second bit lines; and at least one memory cell array in which memory cells connected to said first bit lines and said second bit lines are arranged in a matrix, wherein said memory cell array includes first areas in which said memory cells are arranged, and second areas which are arranged so as to alternate with said first areas and contain no memory cell, and said second areas include areas where connection of said first and second bit lines of a specified number of said bit-line pairs are exchanged.
Claim 2
Dependent Claim
160 words
A dynamic semiconductor memory device comprising: first bit line layer having a plurality of first bit lines; a second bit line layer, which is laminated above said first bit line layer via an insulating layer, having a plurality of second bit lines to form bit-line pairs together with said first bit lines, to build a folded bit-line structure; word lines arranged so as to cross said first bit lines and said second bit lines; and at least one memory cell array in which memory cells connected to said first bit lines and said second bit lines are arranged in a matrix, wherein said memory cell array includes first areas in which said memory cells are arranged, and second areas which are arranged so as to alternate with said first areas and contain no memory cell, and said second areas include areas where connection of said first and second bit lines of a specified number of said bit-line pairs are exchanged.
Claim 3
Dependent Claim
51 words
A dynamic semiconductor memory device according to claim 1, further comprising: transfer gates placed between said memory cells and said first bit lines and connected to the respective first bit lines; and third bit lines connected to said memory cells and connected to said first bit lines via said transfer gates.
Claim 4
Dependent Claim
154 words
A dynamic semiconductor memory device according to claim 1, wherein said second areas include: third areas where for half of said bit-line pairs, said first bit lines cross said second bit lines in three dimensions, and for the remaining half, said first bit lines are connected to said second bit lines, and said second bit lines are connected to said first bit lines; and fourth areas which are adjacent via said first areas to said third areas, where said first bit lines and said second bit lines of said bit-line pairs, for which said first bit lines are connected to said second bit lines and said second bit lines are connected to said first bit lines, cross each other in three dimensions, and for the remaining half of said bit-line pairs, said first bit lines are connected to said second bit lines and said second bit lines are connected to said first bit lines.
Claim 5
Dependent Claim
58 words
A dynamic semiconductor memory device according to claim 2, further comprising: wires coupled to said first bit lines and said second bit lines, one end of each wire being connected via a first contact to said first bit line and the other end being connected via a second contact to said second bit line in said second area.
Claim 6
Dependent Claim
92 words
A dynamic semiconductor memory device according to claim 4, wherein the distance P 1 between one of said first and second contacts and said wire, if the width of and the spacing between said first bit lines and the width of and the spacing between said second bit lines are L 1 , S 1 , and L 2 , S 2 , respectively, fulfills P 1 being substantially equal to S 1 and S 2 , and S 1 ≦P 1 <2S 1 and S 2 P 1 <2S 2 .
Claim 7
Dependent Claim
62 words
A dynamic semiconductor memory device according to claim 3, further comprising: wires coupled to said first bit lines and said second bit lines, one end of each wire being connected via a first contact to said first bit line and the other end being connected via a second contact to said second bit line in said third area and said fourth area.
Claim 8
Dependent Claim
91 words
A dynamic semiconductor memory device according to claim 6, wherein the distance P 1 between one of said first and second contacts and said wire, if the width of and the spacing between said first bit lines and the width of and the spacing between said second bit lines are L 1 , S 1 , and L 2 , S 2 , respectively, fulfills P 1 being substantially equal to S 1 and S 2 and S 1 ≦P 1 <2S 1 and S 2 ≦P 1 <2S 2 .
Claim 9
Dependent Claim
187 words
A dynamic semiconductor memory device comprising: first bit lines; second bit lines which are partially laminated above said first bit lines and, together with said first bit lines, form bit-line pairs to build a folded bit-line structure; word lines arranged so as to cross said first bit lines and said second bit lines; and at least one memory cell array in which memory cells connected to said first bit lines and said second bit lines are arranged in a matrix, wherein said memory cell array includes first areas which are provided with said memory cells, and a plurality of second memory areas which are arranged so as to alternate with said first areas and contain no memory cell, said first bit lines and said second bit lines construct first bit line pairs which are crossed each other in three dimensions in a second area and second bit line pairs which are connected therein, and said first bit line pairs are connected and said second bit line pairs are crossed each other in three dimensions in a third area adjacent via said first area to said second area.
Claim 10
Dependent Claim
187 words
A dynamic semiconductor memory device comprising: first bit lines; second bit lines which are partially laminated above said first bit lines and, together with said first bit lines, form bit-line pairs to build a folded bit-line structure; word lines arranged so as to cross said first bit lines and said second bit lines; and at least one memory cell array in which memory cells connected to said first bit lines and said second bit lines are arranged in a matrix, wherein said memory cell array includes first areas which are provided with said memory cells, and a plurality of second memory areas which are arranged so as to alternate with said first areas and contain no memory cell, said first bit lines and said second bit lines construct first bit line pairs which are crossed each other in three dimensions in a second area and second bit line pairs which are connected therein, and said first bit line pairs are connected and said second bit line pairs are crossed each other in three dimensions in a third area adjacent via said first area to said second area.
Claim 11
Dependent Claim
62 words
A dynamic semiconductor memory device according to claim 8, further comprising: wires coupled to said first bit lines and said second bit lines, one end of each wire being connected via a first contact to said first bit line and the other end being connected via a second contact to said second bit line in said third area and said fourth area.
Claim 12
Dependent Claim
92 words
A dynamic semiconductor memory device according to claim 9, wherein the distance P 1 between one of said first and second contacts and said wire, if the width of and the spacing between said first bit lines and the width of and the spacing between said second bit lines are L 1 , S 1 , and L 2 , S 2 , respectively, fulfills P 1 being substantially equal to S 1 and S 2 , and S 1 ≦P 1 <2S 1 and S 2 ≦P 1 <2S 2 .
Claim 13
Dependent Claim
52 words
A dynamic semiconductor memory device according to claim 8, further comprising: transfer gates placed between said memory cells and said first bit lines and connected to the respective first bit lines; and third bit lines connected to said memory cells and also connected to said first bit lines via said transfer gates.
Claim 14
Dependent Claim
62 words
A dynamic semiconductor memory device according to claim 11, further comprising: wires coupled to said first bit lines and said second bit lines, one end of each wire being connected via a first contact to said first bit line and the other end being connected via a second contact to said second bit line in said third area and said fourth area.
Claim 15
Dependent Claim
93 words
A dynamic semiconductor memory device according to claim 12, wherein the distance P 1 between one of the said first and second contacts and said wire, if the width of and the spacing between said first bit lines and the width of and the spacing between said second bit lines are L 1 , S 1 , and L 2 , S 3 , respectively, fulfills P 1 being substantially equal to S 1 and S 2 , and S 1 ≦P 1 <2S 1 and S 2 ≦P 1 <2S 2 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-11 | 2000-08-12 | 2001-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-11 | 2004-08-12 | 2005-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-11 | 2008-08-12 | 2009-02-11 | $7700.00 | Window Closed / Lapsed |