US5606192A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuits having bipolar transistors and LDD-structured MOSFET
Assignee: NEC Corp
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Filing: 1996-06-13
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Granted: 1997-02-25
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Expires: 2016-06-13
Abstract
Abstract A semiconductor IC comprises an LDD-MOSFET and a bipolar transistor both formed on a common semiconductor substrate. A gate electrode of the MOSFET has a laminated structure including a polysilicon layer, a tungsten silicide layer and another polysilicon layer consecutively formed. The top polysilicon layer functions for protecting the tungsten silicide layer so that tungsten is not back-sputtered to deposit particulates on a base region of the bipolar transistor during an anisotropic etching step for forming sidewall spacers of the gate electrode. Accordingly, a sputter-etch cleaning step for removing tungsten particulates out of the base region is omitted. A BiCMOS IC having an LDD structure and comprising a bipolar transistor with required performance can be manufactured by a simple process.
Inventors
- 👤 Hiroshi Harada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:21
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D64/00; H10D64/60; H10D64/66
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
127 words
A semiconductor integrated circuit comprising: a semiconductor substrate having a main surface; at least one MOSFET formed on said main surface and having a lightly doped drain, a gate electrode laminate and a sidewall spacer formed on a side of said gate electrode laminate adjacent to said lightly doped drain, said gate electrode laminate including a top layer made of a material containing substantially no refractory metal; an insulating layer formed on said gate electrode laminate and said sidewall spacer; and a bipolar transistor formed on said main surface having an emitter electrode formed on and penetrating said insulating layer, said top layer preventing refractory metal particulates from beneath said top layer from contaminating a base region of said bipolar transistor during formation of said sidewall spacer.
Claim 2
Dependent Claim
127 words
A semiconductor integrated circuit comprising: a semiconductor substrate having a main surface; at least one MOSFET formed on said main surface and having a lightly doped drain, a gate electrode laminate and a sidewall spacer formed on a side of said gate electrode laminate adjacent to said lightly doped drain, said gate electrode laminate including a top layer made of a material containing substantially no refractory metal; an insulating layer formed on said gate electrode laminate and said sidewall spacer; and a bipolar transistor formed on said main surface having an emitter electrode formed on and penetrating said insulating layer, said top layer preventing refractory metal particulates from beneath said top layer from contaminating a base region of said bipolar transistor during formation of said sidewall spacer.
Claim 3
Dependent Claim
17 words
A semiconductor integrated circuit as defined in claim 1, wherein said top layer is made of polysilicon.
Claim 4
Dependent Claim
23 words
A semiconductor integrated circuit as defined in claim 1, wherein said gate electrode laminate includes a tungsten silicide layer beneath said top layer.
Claim 5
Dependent Claim
25 words
A semiconductor integrated circuit as defined in claim 3, wherein said gate electrode laminate further includes a second polysilicon layer beneath said tungsten silicide layer.
Claim 6
Dependent Claim
21 words
A semiconductor integrated circuit as defined in claim 1, wherein said at least one MOSFET include a PMOSFET and an NMOSFET.
Claim 7
Dependent Claim
109 words
A semiconductor integrated circuit comprising: a semiconductor substrate having a main surface; at least one MOSFET formed on said main surface and having a lightly doped drain, a gate electrode laminate and a sidewall spacer formed on a side of said gate electrode laminate adjacent to said lightly doped drain, said gate electrode laminate including a first polysilicon layer, a tungsten silicide layer and a second polysilicon layer consecutively formed in this order above said main surface; and a bipolar transistor formed on said main surface, said second polysilicon layer preventing tungsten silicide particulates from contaminating a base region of said bipolar transistor during formation of said sidewall spacer.
Claim 8
Dependent Claim
109 words
A semiconductor integrated circuit comprising: a semiconductor substrate having a main surface; at least one MOSFET formed on said main surface and having a lightly doped drain, a gate electrode laminate and a sidewall spacer formed on a side of said gate electrode laminate adjacent to said lightly doped drain, said gate electrode laminate including a first polysilicon layer, a tungsten silicide layer and a second polysilicon layer consecutively formed in this order above said main surface; and a bipolar transistor formed on said main surface, said second polysilicon layer preventing tungsten silicide particulates from contaminating a base region of said bipolar transistor during formation of said sidewall spacer.
Claim 9
Dependent Claim
21 words
A semiconductor integrated circuit as defined in claim 6, wherein said at least one MOSFET include a PMOSFET and an NMOSFET.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 2000-02-25 | 2000-08-26 | 2001-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-25 | 2004-08-26 | 2005-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-25 | 2008-08-26 | 2009-02-25 | $7700.00 | Window Closed / Lapsed |