Interleaving pixel data for a memory display interface

Claim 2

A memory display interface for a graphics subsystem, comprising: pixel processing pipeline capable of processing a set of N pixel data values in parallel synchronized by a pipeline clock wherein N is a number greater than zero; input stage coupled to receive a set of input pixel data values over a video bus, the input stage coupled to transfer the input pixel data values into the pixel processing pipeline such that N of the input pixel data values are provided to the pixel processing pipeline during each of a plurality of cycles of the pipeline clock; clock circuit that generates the pipeline clock and that generates a first shift clock to synchronize the input pixel data values on the video bus, the first shift clock and the pipeline clock each having a frequency determined by a frequency of a display device for the graphics subsystem and by a width of each input pixel data value on the video bus and by the number N.

Claim 3

The memory display interface of claim 1, wherein a final pixel processing stage of the pixel processing pipeline transfers a set of N/2 pixel data values over a pixel bus for the display device.

Claim 4

The memory display interface of claim 2, wherein the clock circuit receives a pixel clock that synchronizes the N/2 pixel data values on the pixel bus, and generates the pipeline clock to synchronize the pixel processing pipeline at a frequency equal to one half a frequency of the pixel clock.

Claim 5

The memory display interface of claim 3, wherein the width of each input pixel data value comprises 32 bits such that the clock circuit generates the frequency of the first shift clock at the frequency of the pipeline clock.

Claim 6

The memory display interface of claim 3, wherein the width of each input pixel data value comprises 16 bits such that the clock circuit generates the frequency of the first shift clock at one half the frequency of the pipeline clock.

Claim 7

The memory display interface of claim 3, wherein the width of each input pixel data value comprises 8 bits such that the clock circuit generates the frequency of the first shift clock at one fourth the frequency of the pipeline clock.

Claim 8

The memory display interface of claim 3, wherein the clock circuit generates a second shift clock to synchronize the input pixel data values on the video bus, the second shift clock having a frequency determined by the frequency of the display device and by the width of each input pixel data value on the video bus and by the number N and by a single or dual video memory mode for the graphics subsystem.

Claim 9

The memory display interface of claim 7, wherein the width of each input pixel data value comprises 32 bits such that the clock circuit generates the frequency of the first and second shift clocks each at one half the frequency of the pipeline clock.

Claim 10

The memory display interface of claim 7, wherein the width of each input pixel data value comprises 16 bits such that the clock circuit generates the frequency of the first and second shift clocks each at one fourth the frequency of the pipeline clock.

Claim 11

The memory display interface of claim 7, wherein the width of each input pixel data value comprises 8 bits such that the clock circuit generates the frequency of the first and second shift clocks each at one eighth the frequency of the pipeline clock.

Claim 12

A graphics subsystem, comprising: first and second video memory banks each coupled to store a set of pixel data; memory display interface coupled receive a set of input pixel data values from the video memory banks over a video bus, the memory display interface processing a set of N pixel data values in parallel synchronized by a pipeline clock wherein N is a number greater than zero, and transferring a set of N/2 pixel data values over a pixel bus, the memory display interface generating a first shift clock to read the input pixel data values from the first video memory bank and generating a second shift clock to read the input pixel data values from the second video memory bank, the first and second shift clocks and the pipeline clock each having a frequency determined by a frequency of a display device for the graphics subsystem and by a width of the pixel data in the video memory banks and by the number N; digital-to-analog converter that generates a set of video signals for the display device and that generates a pixel clock to synchronize the pixel bus according to a video clock for the display device.

Claim 13

A graphics subsystem, comprising: first and second video memory banks each coupled to store a set of pixel data; memory display interface coupled receive a set of input pixel data values from the video memory banks over a video bus, the memory display interface processing a set of N pixel data values in parallel synchronized by a pipeline clock wherein N is a number greater than zero, and transferring a set of N/2 pixel data values over a pixel bus, the memory display interface generating a first shift clock to read the input pixel data values from the first video memory bank and generating a second shift clock to read the input pixel data values from the second video memory bank, the first and second shift clocks and the pipeline clock each having a frequency determined by a frequency of a display device for the graphics subsystem and by a width of the pixel data in the video memory banks and by the number N; digital-to-analog converter that generates a set of video signals for the display device and that generates a pixel clock to synchronize the pixel bus according to a video clock for the display device.

Claim 14

The graphics subsystem of claim 11, wherein the memory display interface comprises: pixel processing pipeline comprising a set of pixel processing stages each capable of processing the N pixel data values in parallel, the pixel processing pipeline having a final pixel processing stage that transfers the N/2 pixel data values over the pixel bus; input stage coupled to receive the input pixel data values from the video memory banks over the video bus, the input stage coupled to transfer the input pixel data values into the pixel processing pipeline such that N of the input pixel data values are provided to the pixel processing pipeline during each of a plurality of cycles of the pipeline clock; clock circuit that generates the pipeline clock and that generates the first and second shift clocks each having a frequency determined by the frequency of the display device as indicated by a frequency of the pixel clock and by the width of the pixel data in the video memory banks and by the number N, the clock circuit further generating a first and a second serial output enable signal to enable and disable the first and second video memory banks.

Claim 15

The graphics subsytem of claim 12, wherein the clock circuit receives the pixel clock that synchronizes the N/2 pixel data values on the pixel bus, and generates the pipeline clock to synchronize the pixel processing pipeline at a frequency equal to one half a frequency of the pixel clock.

Claim 16

The graphics subsystem of claim 13, wherein the width of the pixel data comprises 32 bits such that the clock circuit generates the frequency of the first and second shift clocks each at one half the frequency of the pipeline clock.

Claim 17

The graphics subsystem of claim 13, wherein the width of the pixel data comprises 16 bits such that the clock circuit generates the frequency of the first and second shift clocks each at one fourth the frequency of the pipeline clock.

Claim 18

The graphics subsystem of claim 13, wherein the width of the pixel data comprises 8 bits such that the clock circuit generates the frequency of the first and second shift clocks each at one eighth the frequency of the pipeline clock.

Claim 19

The graphics subsystem of claim 13, wherein the width of the pixel data comprises 32 bits such that the clock circuit generates the frequency of the first shift clock equal to the frequency of the pipeline clock.

Claim 20

The graphics subsystem of claim 13, wherein the width of the pixel data comprises 16 bits such that the clock circuit generates the frequency of the first shift clock at one half the frequency of the pipeline clock.

Claim 21

The graphics subsystem of claim 13, wherein the width of the pixel data comprises 8 bits such that the clock circuit generates the frequency of the first shift clock at one fourth the frequency of the pipeline clock.