US5608679A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fast internal reference cell trimming for flash EEPROM memory
Assignee: Intel Corp
•
Filing: 1996-01-31
•
Granted: 1997-03-04
•
Expires: 2016-01-31
Abstract
Abstract A method for storing a charge on memory devices which includes the steps of providing a first charging pulse to a memory device to charge the device to a first level less than a final level; testing the value of the charge to determine whether the charge is greater than the first level; if the value of the charge is less than the first level, providing a second set of charging pulses to the memory device, each of the pulses of the second set of pulses having a duration which is a fraction of the duration of the first pulse and a value sufficient to charge the device to the first level; testing the value of the charge to determine whether the charge is greater than the first level after each pulse of the second set of pulses; and once the charge has tested greater than the first level, providing a third set of charging pulses to terminals of the memory device, each of the pulses of the third set of pulses having a duration which is a fraction of the duration of the pulses of the second set of pulses and a value such that the charge furnished by each pulse is approximately equal to an allowable variation of the charge from the final value.
Inventors
- 👤 James Q. Mi
- 👤 Johnny Javanifard
- 👤 Dennis Dilley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:52
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C29/00; G11C29/04; G11C29/50; G11C29/52; G06; G06F; G06F2201/00; G06F2201/81; G11C16/04; G11C2029/5006; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621; G11C2211/563; G11C2211/5634
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
316 words
A method for storing a charge on a memory device comprising the steps of: providing a first charging pulse to terminals of a memory device, the first charging pulse having a first charging voltage and a first duration such that the memory device stores close to a first amount of charge that is less than a target amount of charge; testing the memory device to determine whether the memory device stores more than the first amount of charge; if the first amount of charge is less than a first level, providing a second set of charging pulses to terminals of the memory device to charge the memory device close to the first level, each charging pulse of the second set of charging pulses having a second duration which is less than the first duration and a second charging voltage having a second amount of charge such that the memory device stores close to the first amount of charge; testing the memory device to determine whether the memory device stores more than the first amount of charge after each charging pulse of the second set of charging pulses; once the memory device has been determined as storing more than the first amount of charge, providing a third set of charging pulses to terminals of the memory device until the memory device stores the target amount of charge, each of the charging pulses of the third set of charging pulses having a third duration which is less than the second duration and a third charging voltage such that a third amount of charge furnished by each charging pulse of the third set of charging pulses is approximately equal to an allowable variation from the target amount of charge; and testing the memory device to determine whether the memory device stores more than the target amount of charge after each charging pulse of the third set of charging pulses.
Claim 2
Independent Claim
316 words
A method for storing a charge on a memory device comprising the steps of: providing a first charging pulse to terminals of a memory device, the first charging pulse having a first charging voltage and a first duration such that the memory device stores close to a first amount of charge that is less than a target amount of charge; testing the memory device to determine whether the memory device stores more than the first amount of charge; if the first amount of charge is less than a first level, providing a second set of charging pulses to terminals of the memory device to charge the memory device close to the first level, each charging pulse of the second set of charging pulses having a second duration which is less than the first duration and a second charging voltage having a second amount of charge such that the memory device stores close to the first amount of charge; testing the memory device to determine whether the memory device stores more than the first amount of charge after each charging pulse of the second set of charging pulses; once the memory device has been determined as storing more than the first amount of charge, providing a third set of charging pulses to terminals of the memory device until the memory device stores the target amount of charge, each of the charging pulses of the third set of charging pulses having a third duration which is less than the second duration and a third charging voltage such that a third amount of charge furnished by each charging pulse of the third set of charging pulses is approximately equal to an allowable variation from the target amount of charge; and testing the memory device to determine whether the memory device stores more than the target amount of charge after each charging pulse of the third set of charging pulses.
Claim 3
Dependent Claim
20 words
A method as claimed in claim 1 in which the memory device is a flash EEPROM field effect transistor device.
Claim 4
Dependent Claim
36 words
A method as claimed in claim 2 in which all charging pulses are applied to a gate terminal of the flash EEPROM field effect transistor device while drain and source terminals are held at constant values.
Claim 5
Dependent Claim
81 words
A method as claimed in claim 3 in which the first charging pulse has the first charging voltage sufficient to place the memory device in a saturation range of operation, each charging pulse of the second set of charging pulses having a charging voltage that is greater than a charging voltage of an immediately preceding charging pulse, and wherein the third charging voltage is equal to a charging voltage of a last charging pulse of the second set of charging pulses.
Claim 6
Independent Claim
327 words
A method for storing a charge on a flash EEPROM field effect memory device comprising the steps of: providing a first charging pulse to a gate terminal of the memory device while holding drain and source terminals constant, the first charging pulse having a first charging voltage and a first duration such that the memory device stores close to a first amount of charge that is less than a target amount of charge, the first amount of charge being sufficient to place the memory device in the saturation range of operation; testing the memory device to determine whether the memory device stores more than the first amount of charge; if the memory device stores less than the first amount of charge, providing a second set of charging pulses to the gate terminal of the memory device, each charging pulse of the second set of charging pulses having a second duration which is less than the first duration and a second charging voltage having a second amount of charge such that the memory device stores close to the first amount of charge; testing the memory device to determine whether the memory device stores more than the first amount of charge after each charging pulse of the second set of charging pulses; once the memory device has been determined as storing more than the first amount of charge, providing a third set of charging pulses to terminals of the memory device, each charging pulse of the third set of charging pulses having a third duration which is less that the second duration and a third charging voltage such that a third amount of charge furnished by each charging pulse of the third set of charging pulses is approximately equal to an allowable variation from the target amount of charge; and testing the memory device to determine whether the memory device stores more than the target amount of charge after each charging pulse of the third set of charging pulses.
Claim 7
Independent Claim
327 words
A method for storing a charge on a flash EEPROM field effect memory device comprising the steps of: providing a first charging pulse to a gate terminal of the memory device while holding drain and source terminals constant, the first charging pulse having a first charging voltage and a first duration such that the memory device stores close to a first amount of charge that is less than a target amount of charge, the first amount of charge being sufficient to place the memory device in the saturation range of operation; testing the memory device to determine whether the memory device stores more than the first amount of charge; if the memory device stores less than the first amount of charge, providing a second set of charging pulses to the gate terminal of the memory device, each charging pulse of the second set of charging pulses having a second duration which is less than the first duration and a second charging voltage having a second amount of charge such that the memory device stores close to the first amount of charge; testing the memory device to determine whether the memory device stores more than the first amount of charge after each charging pulse of the second set of charging pulses; once the memory device has been determined as storing more than the first amount of charge, providing a third set of charging pulses to terminals of the memory device, each charging pulse of the third set of charging pulses having a third duration which is less that the second duration and a third charging voltage such that a third amount of charge furnished by each charging pulse of the third set of charging pulses is approximately equal to an allowable variation from the target amount of charge; and testing the memory device to determine whether the memory device stores more than the target amount of charge after each charging pulse of the third set of charging pulses.
Claim 8
Dependent Claim
60 words
A method as claimed in claim 5 in which each charging pulse of the second set of charging pulses has a charging voltage that is greater than a charging voltage of an immediately preceding charging pulse, and wherein the third charging voltage is equal to a charging voltage of a last charging pulse of the second set of charging pulses.
Claim 9
Dependent Claim
28 words
A method as claimed in claim 5 wherein the second duration is equal to, one-forth the first duration, and wherein the third duration is one-tenth the second duration.
Claim 10
Dependent Claim
37 words
A method as claimed in claim 5 in which the charging voltage of each charging pulse of the second set of charging pulses is one-tenth volt greater than the charging voltage of the immediately preceding charging pulse.
Claim 11
Independent Claim
179 words
A method for programming a memory cell such that a memory device stores close to a target amount of charge, comprising the steps of: applying a first charging pulse to the memory device for a first duration such that the memory device stores a first amount of charge that is less than the target amount of charge; applying a second set of charging pulses to the memory device such that the memory device stores a second amount of charge that is less than the target amount of charge and greater than the first amount of charge, wherein each charging pulse of the second set of charging pulses is applied for a second duration that is less than the first duration; and applying a third set of charging pulses to the memory device such that the memory device stores a third amount of charge that is within an allowable variation of the target amount of charge, wherein each charging pulse of the third set of charging pulses is applied for a third duration that is less than the second duration.
Claim 12
Independent Claim
179 words
A method for programming a memory cell such that a memory device stores close to a target amount of charge, comprising the steps of: applying a first charging pulse to the memory device for a first duration such that the memory device stores a first amount of charge that is less than the target amount of charge; applying a second set of charging pulses to the memory device such that the memory device stores a second amount of charge that is less than the target amount of charge and greater than the first amount of charge, wherein each charging pulse of the second set of charging pulses is applied for a second duration that is less than the first duration; and applying a third set of charging pulses to the memory device such that the memory device stores a third amount of charge that is within an allowable variation of the target amount of charge, wherein each charging pulse of the third set of charging pulses is applied for a third duration that is less than the second duration.
Claim 13
Dependent Claim
173 words
The method of claim 9, further comprising the steps of: testing the memory device after applying the first charging pulse to determine whether the first amount of charge exceeds the second amount of charge, wherein the step of applying the second set of charging pulses is not performed if the first amount of charge exceeds the second amount of charge; testing the memory device after applying each charging pulse of the second set of charging pulses to determine whether the memory device stores the second amount of charge, wherein the charging pulses of the second set of charging pulses continue to be applied until the memory device is determined as storing the second amount of charge; and testing the memory device after applying each charging pulse of the third set of charging pulses to determine whether the memory device stores the third amount of charge, wherein the charging pulses of the third set of charging pulses continue to be applied until the memory device is determined as storing the third amount of charge.
Claim 14
Dependent Claim
32 words
The method of claim 10, wherein a charging voltage of each charging pulse of the second set of charging pulses is greater than a charging voltage of an immediately previous charging pulse.
Claim 15
Dependent Claim
48 words
The method of claim 9, wherein the memory device is a flash EEPROM memory cell and the first charging pulse has a first charging voltage, the first charging voltage and the first duration are selected such that the flash EEPROM memory cell is placed in a saturation range.
Claim 16
Dependent Claim
25 words
The method of claim 12, wherein the second duration is approximately one-fourth the first duration, and the third duration is approximately one-tenth the second duration.
Claim 17
Dependent Claim
34 words
The method of claim 13, wherein a charging voltage of each charging pulse of the second set of charging pulses is one-tenth volt greater than a charging voltage of an immediately previous charging pulse.
Claim 18
Dependent Claim
182 words
A circuit for programming a memory cell such that a memory device stores close to a target amount of charge, comprising: means for applying a first charging pulse to the memory device for a first duration such that the memory device stores a first amount of charge that is less than the target amount of charge; means for applying a second set of charging pulses to the memory device such that the memory device stores a second amount of charge that is less than the target amount of charge and greater than the first amount of charge, wherein each charging pulse of the second set of charging pulses is applied for a second duration that is less than the first duration; and means for applying a third set of charging pulses to the memory device such that the memory device stores a third amount of charge that is within an allowable variation of the target amount of charge, wherein each charging pulse of the third set of charging pulses is applied for a third duration that is less than the second duration.
Claim 19
Dependent Claim
182 words
A circuit for programming a memory cell such that a memory device stores close to a target amount of charge, comprising: means for applying a first charging pulse to the memory device for a first duration such that the memory device stores a first amount of charge that is less than the target amount of charge; means for applying a second set of charging pulses to the memory device such that the memory device stores a second amount of charge that is less than the target amount of charge and greater than the first amount of charge, wherein each charging pulse of the second set of charging pulses is applied for a second duration that is less than the first duration; and means for applying a third set of charging pulses to the memory device such that the memory device stores a third amount of charge that is within an allowable variation of the target amount of charge, wherein each charging pulse of the third set of charging pulses is applied for a third duration that is less than the second duration.
Claim 20
Dependent Claim
176 words
The circuit of claim 15, further comprising: means for testing the memory device after applying the first charging pulse to determine whether the first amount of charge exceeds the second amount of charge, wherein said means for applying the second set of charging pulses is not performed if the first amount of charge exceeds the second amount of charge; means for testing the memory device after applying each charging pulse of the second set of charging pulses to determine whether the memory device stores the second amount of charge, wherein the charging pulses of the second set of charging pulses continue to be applied until the memory device is determined as storing the second amount of charge; and means for testing the memory device after applying each charging pulse of the third set of charging pulses to determine whether the memory device stores the third amount of charge, wherein the charging pulses of the third set of charging pulses continue to be applied until the memory device is determined as storing the third amount of charge.
Claim 21
Dependent Claim
32 words
The circuit of claim 16, wherein a charging voltage of each charging pulse of the second set of charging pulses is greater than a charging voltage of an immediately previous charging pulse.
Claim 22
Dependent Claim
48 words
The circuit of claim 15, wherein the memory device is a flash EEPROM memory cell and the first charging pulse has a first charging voltage, the first charging voltage and the first duration are selected such that the flash EEPROM memory cell is placed in a saturation range.
Claim 23
Dependent Claim
25 words
The circuit of claim 18, wherein the second duration is approximately one-fourth the first duration, and the third duration is approximately one-tenth the second duration.
Claim 24
Dependent Claim
34 words
The circuit of claim 15, wherein a charging voltage of each charging pulse of the second set of charging pulses is one-tenth volt greater than a charging voltage of an immediately previous charging pulse.
References Cited (Backward Citations)
US4357685A
Cited
US4460982A
Cited
US5053990A
Cited
US5222046A
Cited
US5371703A
Cited
US5386388A
Cited
US5218569A
Cited
US5394362A
Cited
US5394371A
Cited
US5381374A
Cited
US5444656A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-03 | 2000-09-02 | 2001-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-03 | 2004-09-02 | 2005-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-03 | 2008-09-02 | 2009-03-04 | $7700.00 | Window Closed / Lapsed |