US5610849A
Expired / Lapsed
US
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Real time two-dimensional discrete cosine transform/inverse discrete cosine transform circuit
Assignee: United Microelectronics Corp
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Filing: 1995-06-23
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Granted: 1997-03-11
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Expires: 2015-06-23
Abstract
Abstract A 2-D DCT/IDCT circuit comprises a rate buffer, a multiplexer, a one-dimensional DCT/IDCT processor, a transpose buffer and an inverse rate buffer. The data input rate of the rate buffer and the output rate of the inverse rate buffer are a first rate, while the transform process, which is carried out between the rate buffer and the inverse rate buffer by the 1-D DCT/IDCT processor, is at a second rate. Since the second rate is approximately two times the first rate, the 2-D DCT/IDCT circuit can satisfy the requirement of high speed operation. Moreover, since the 2-D DCT/IDCT circuit according the present invention provides a specific arrangement of the order of input/output data, the hardware structure is simplified, thereby making it easy to realize in a VLSI circuit.
Inventors
- 👤 Po-Chuan Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:22
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/14; G06F17/147
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
165 words
A real time two-dimensional discrete cosine transform (DCT)/inverse discrete cosine transform (IDCT) circuit comprising: a rate buffer for inputting an N×N data at a first rate and outputting said data at a second rate; a multiplexer for providing one of a first data path and a second data path for data transmission, wherein said first data path is provided for said data from said rate buffer during a first time period, while during a second time period, said second data path is provided for transposed data; a one-dimensional (1-D) DCT/IDCT processor for performing 1-D DCT/IDCT of data from said data paths of said multiplexer; a transpose buffer for transposing data from said 1-D DCT/IDCT processor, wherein said transposed data is generated by said transpose buffer and is stored therein during said first time period; and an inverse rate buffer for acquiring data from said transpose buffer, during said second time period, at said second rate, and outputting an N×N transformed data at said first rate.
Claim 2
Dependent Claim
165 words
A real time two-dimensional discrete cosine transform (DCT)/inverse discrete cosine transform (IDCT) circuit comprising: a rate buffer for inputting an N×N data at a first rate and outputting said data at a second rate; a multiplexer for providing one of a first data path and a second data path for data transmission, wherein said first data path is provided for said data from said rate buffer during a first time period, while during a second time period, said second data path is provided for transposed data; a one-dimensional (1-D) DCT/IDCT processor for performing 1-D DCT/IDCT of data from said data paths of said multiplexer; a transpose buffer for transposing data from said 1-D DCT/IDCT processor, wherein said transposed data is generated by said transpose buffer and is stored therein during said first time period; and an inverse rate buffer for acquiring data from said transpose buffer, during said second time period, at said second rate, and outputting an N×N transformed data at said first rate.
Claim 3
Dependent Claim
18 words
The DCT/IDCT circuit of claim 1, wherein said second rate is two times faster than said first rate.
Claim 4
Dependent Claim
26 words
The DCT/IDCT circuit of claim 1, wherein said 1-D DCT/IDCT processor is a two-speed DCT/IDCT processor whose throughput rate is not smaller than said second rate.
Claim 5
Dependent Claim
20 words
The DCT/IDCT circuit of claim 1, wherein said rate buffer is provided with various address modes for said N×N data.
Claim 6
Dependent Claim
22 words
The DCT/IDCT circuit of claim 1, wherein said inverse rate buffer is provided with various address modes for said N×N transformed data.
Claim 7
Dependent Claim
24 words
The DCT/IDCT circuit of claim 1, wherein two signals with different frequencies are provided at the input and output ends of said rate buffer.
Claim 8
Dependent Claim
25 words
The DCT/IDCT circuit of claim 1, wherein two signals with different frequencies are provided at the input and output ends of said inverse rate buffer.
Claim 9
Dependent Claim
25 words
The DCT/IDCT circuit of claim 1, wherein two counters of different operating rates are provided at the input and output ends of said rate buffer.
Claim 10
Dependent Claim
26 words
The DCT/IDCT circuit of claim 1, wherein two counters of different operating rates are provided at the input and output ends of said inverse rate buffer.
Claim 11
Dependent Claim
14 words
The DCT/IDCT circuit of claim 1, wherein said rate buffer comprises a dual-port device.
Claim 12
Dependent Claim
15 words
The DCT/IDCT circuit of claim 1, wherein said inverse rate buffer comprises a dual-port device.
Claim 13
Dependent Claim
18 words
The DCT/IDCT circuit of claim 1, wherein said rate buffer comprises a dual-port static random access memory (SRAM).
Claim 14
Dependent Claim
15 words
The DCT/IDCT circuit of claim 1, wherein said inverse rate buffer comprises a dual-port SRAM.
Claim 15
Dependent Claim
17 words
The DCT/IDCT circuit of claim 1 having a latency less than 2N-1 cycles of the second rate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-10 | 2000-09-09 | 2001-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-10 | 2004-09-09 | 2005-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-10 | 2008-09-09 | 2009-03-11 | $7700.00 | Window Closed / Lapsed |