US5612234A
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Method for manufacturing a thin film transistor
Assignee: LG Display Co Ltd
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Filing: 1995-10-04
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Granted: 1997-03-18
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Expires: 2015-10-04
Abstract
Abstract A thin film transistor for incorporation into an active-matrix liquid crystal display includes an active layer provided on a substrate. An electrode insulating layer is formed on the active layer, and a gate electrode including first and second gate layers is provided on the electrode insulating layer. The second gate layer overlies the first gate layer and has a width greater than the first gate layer. LDD regions, self-aligned with the second gate layer are provided in the active layer adjacent source and drain regions. The active layer further including a channel region located under the first gate layer and offset regions located under portions of the second gate layer extending beyond the first gate layer at opposite sides of the channel region. In the manufacture of the thin film transistor, an active layer is formed on a substrate; electrode insulating layer is formed on the active layer; oxidizable first gate electrode and a non-oxidizable second gate electrode of the same widths are stacked on the electrode insulating layer; low-concentration impurity ions are implanted in the active layer using the second gate electrode as a mask; sides of the first electrode, to form oxide layers that reduce the width of the first gate electrode; and implanting high-concentration impurity ions, using the second gate electrode and the oxide layers as implantation masks.
Inventors
- 👤 Yong M. Ha
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:53
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6721
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
190 words
A method of fabricating a semiconductor device comprising the steps of: forming a semiconductor layer; forming an insulative layer on said semiconductor layer; forming a first gate layer on said insulative layer; forming a second gate layer on said first gate layer; patterning said first and second gate layers so that said first gate layer has a width substantially the same as a width of said second gate layer; introducing a first amount of first impurities into said semiconductor layer using said first and second gate layers as a mask, thereby forming a doped region in said semiconductor layer; oxidizing an edge of said first gate layer to the exclusion of said second gate layer, thereby reducing a width of said first gate layer; and introducing a second amount of second impurities into said semiconductor layer using said oxidized edge of said first gate layer as a mask, said second amount is greater than said first amount, wherein said reduced width of said first gate layer defines a gate underlying region in said semiconductor layer, and said doped region is spaced from said gate underlying region in said semiconductor layer.
Claim 2
Independent Claim
190 words
A method of fabricating a semiconductor device comprising the steps of: forming a semiconductor layer; forming an insulative layer on said semiconductor layer; forming a first gate layer on said insulative layer; forming a second gate layer on said first gate layer; patterning said first and second gate layers so that said first gate layer has a width substantially the same as a width of said second gate layer; introducing a first amount of first impurities into said semiconductor layer using said first and second gate layers as a mask, thereby forming a doped region in said semiconductor layer; oxidizing an edge of said first gate layer to the exclusion of said second gate layer, thereby reducing a width of said first gate layer; and introducing a second amount of second impurities into said semiconductor layer using said oxidized edge of said first gate layer as a mask, said second amount is greater than said first amount, wherein said reduced width of said first gate layer defines a gate underlying region in said semiconductor layer, and said doped region is spaced from said gate underlying region in said semiconductor layer.
Claim 3
Dependent Claim
16 words
A method in accordance with claim 1, wherein said first and second impurities are the same.
Claim 4
Dependent Claim
17 words
A method in accordance with claim 1, wherein said oxidizing step further includes a step of anodization.
Claim 5
Dependent Claim
31 words
A method in accordance with claim 1, wherein said step of introducing said first amount of first impurities includes a step of ion implanting said first impurities into said semiconductor layer.
Claim 6
Dependent Claim
31 words
A method in accordance with claim 1, wherein said step of introducing said first amount of first impurities includes a step of ion doping said first impurities into said semiconductor layer.
Claim 7
Dependent Claim
31 words
A method in accordance with claim 1, wherein said step of introducing said second amount of second impurities includes a step of ion implanting said second impurities into said semiconductor layer.
Claim 8
Dependent Claim
31 words
A method in accordance with claim 1, wherein said step of introducing said second amount of second impurities includes a step of ion doping said second impurities into said semiconductor layer.
Claim 9
Independent Claim
234 words
A method of manufacturing a thin film transistor comprising the steps of: forming an active layer on a substrate; forming an gate insulating layer on said active layer; forming a gate electrode having an oxidizable first gate layer of a first width on said gate insulating layer and a non-oxidizing second gate layer of a second width equal to the first width of said first gate layer; implanting impurity ions of a first dose using said second gate layer as a mask to thereby form a first plurality of impurity regions in said active layer of a first concentration; oxidizing a first side of said first gate layer to form a first oxide layer and a second side of said first gate layer opposite said first side of said first gate layer to form a second oxide layer, thereby to reduce a width of said first electrode; and implanting impurity ions of a second dose using said second electrode and said first and second oxide layers as an implantation mask to form a second plurality of impurity regions in said active layer, said second plurality of impurity regions having a second concentration greater than said first concentration, wherein said reduced width of said first gate layer defines a gate underlying region in said active layer, and said first plurality of impurity regions each being spaced from said gate underlying region in said active layer.
Claim 10
Independent Claim
234 words
A method of manufacturing a thin film transistor comprising the steps of: forming an active layer on a substrate; forming an gate insulating layer on said active layer; forming a gate electrode having an oxidizable first gate layer of a first width on said gate insulating layer and a non-oxidizing second gate layer of a second width equal to the first width of said first gate layer; implanting impurity ions of a first dose using said second gate layer as a mask to thereby form a first plurality of impurity regions in said active layer of a first concentration; oxidizing a first side of said first gate layer to form a first oxide layer and a second side of said first gate layer opposite said first side of said first gate layer to form a second oxide layer, thereby to reduce a width of said first electrode; and implanting impurity ions of a second dose using said second electrode and said first and second oxide layers as an implantation mask to form a second plurality of impurity regions in said active layer, said second plurality of impurity regions having a second concentration greater than said first concentration, wherein said reduced width of said first gate layer defines a gate underlying region in said active layer, and said first plurality of impurity regions each being spaced from said gate underlying region in said active layer.
Claim 11
Dependent Claim
21 words
A method of manufacturing a thin film transistor in accordance with claim 8, wherein said substrate is a transparent insulative substrate.
Claim 12
Dependent Claim
32 words
A method of manufacturing a thin film transistor in accordance with claim 8, wherein said step of oxidizing said first and second sides of the first gate layer includes an anodizing process.
Claim 13
Dependent Claim
54 words
A method of manufacturing a TFT in accordance with claim 10, further comprising the steps of: connecting said gate electrode to a gate line; coupling an end of said gate line to a shorting bar; performing said anodizing using said shorting bar as an anodization electrode; and removing said shorting bar after said anodizing.
Claim 14
Dependent Claim
34 words
A method of manufacturing a thin film transistor as claimed in claim 8, wherein said first and second plurality of impurity regions have a conductivity type selected from a group of n and p.
Claim 15
Dependent Claim
28 words
A method of manufacturing a thin film transistor in accordance with claim 8, wherein said first dosage is selected from a range of 0-10 14 /cm 2 .
Claim 16
Dependent Claim
30 words
A method of manufacturing a thin film transistor in accordance with claim 8, wherein said oxidizable material is selected from a group including aluminum, tantalum and aluminum-tantalum, molybdenum, and aluminum-molybdenum.
Claim 17
Dependent Claim
21 words
A method of manufacturing a thin film transistor in accordance with claim 8, wherein said second gate layer includes non-anodizing material.
Claim 18
Dependent Claim
33 words
A method of manufacturing a thin film transistor in accordance with claim 15, wherein said non-anodizing material is selected from a group including chrome, semiconductor, silicon oxide, silicon nitride and a photosensitive layer.
Claim 19
Dependent Claim
98 words
A method of manufacturing a thin film transistor in accordance with claim 8, further comprising the steps of: forming an interlevel insulating layer on said gate electrode insulating layer, said first oxide layer, said second oxide layers and said second gate electrode; patterning said interlevel insulating layer and gate insulating layer to form a plurality of contact holes respectively extending to each of said second plurality of impurity regions; forming and patterning a conductive layer in said plurality of contact holes; and forming a passivation insulating layer on said patterned interlevel insulating layer and said patterned conductive layer.
Claim 20
Independent Claim
225 words
A method of manufacturing a thin film transistor comprising the steps of: forming an active layer on a substrate; forming an gate insulating layer on said active layer; forming a gate electrode including an oxidizable first gate layer of a first width on said gate insulating layer and a non-oxidizable second gate layer of a second width equal to the first width of said first gate layer; implanting impurity ions at a first dose using said second electrode as a mask, to thereby form a first plurality of impurity regions of a first concentration in said active layer; forming a sidewall spacer against a first side of said first gate layer and a side of said second gate layer; oxidizing a second side of said first gate layer opposite said first side to form an oxide layer, thereby reducing the first width of said first electrode; and implanting impurity ions at a second dose using said second electrode and said oxide layer as an implantation mask to form a second plurality of impurity regions in said active layer of a second concentration greater than said first concentration, wherein said reduced first width of said first gate layer defines a gate underlying region in said active layer, and said first plurality of impurity regions each being spaced from said gate underlying region in said active layer.
Claim 21
Independent Claim
225 words
A method of manufacturing a thin film transistor comprising the steps of: forming an active layer on a substrate; forming an gate insulating layer on said active layer; forming a gate electrode including an oxidizable first gate layer of a first width on said gate insulating layer and a non-oxidizable second gate layer of a second width equal to the first width of said first gate layer; implanting impurity ions at a first dose using said second electrode as a mask, to thereby form a first plurality of impurity regions of a first concentration in said active layer; forming a sidewall spacer against a first side of said first gate layer and a side of said second gate layer; oxidizing a second side of said first gate layer opposite said first side to form an oxide layer, thereby reducing the first width of said first electrode; and implanting impurity ions at a second dose using said second electrode and said oxide layer as an implantation mask to form a second plurality of impurity regions in said active layer of a second concentration greater than said first concentration, wherein said reduced first width of said first gate layer defines a gate underlying region in said active layer, and said first plurality of impurity regions each being spaced from said gate underlying region in said active layer.
Claim 22
Dependent Claim
29 words
A method of manufacturing a thin film transistor in accordance with claim 18, wherein said oxidization of the second side of said first gate layer uses an anodization process.
Claim 23
Dependent Claim
22 words
A method of manufacturing a thin film transistor in accordance with claim 18, further comprising the step of removing said sidewall spacer.
Claim 24
Dependent Claim
56 words
A method of manufacturing a TFT in accordance with claim 19, further comprising the steps of: connecting said gate electrode to a gate line; coupling an end of said gate line to a shorting bar; performing said anodizing process using said shorting bar as an anodization electrode; and removing said shorting bar after said anodizing process.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-03-17 | 2000-09-16 | 2001-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-17 | 2004-09-16 | 2005-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-17 | 2008-09-16 | 2009-03-18 | $7700.00 | Window Closed / Lapsed |