US5615162A — Selective power to memory

Claim 1

Independent Claim 71 words

A memory associated with a mircoprocessor comprising: a memory cell array; and a switch coupled between said memory cell array and a supply voltage, said switch controllably connecting and disconnecting said memory cell array and said supply voltage in response to a selected state of a first control signal and a second control signal generated by said microprocessor wherein said first control signal and said second control signal may independently vary.

Claim 2

Dependent Claim 71 words

A memory associated with a mircoprocessor comprising: a memory cell array; and a switch coupled between said memory cell array and a supply voltage, said switch controllably connecting and disconnecting said memory cell array and said supply voltage in response to a selected state of a first control signal and a second control signal generated by said microprocessor wherein said first control signal and said second control signal may independently vary.

Claim 3

Dependent Claim 56 words

The memory, as set forth in claim 1, further comprising a logic circuit receiving said first control signal as a standby control signal and said second control signal as a data retention control signal, an output of said logic circuit controlling said switch in response to selected states of said standby and data retention control signals.

Claim 4

Dependent Claim 55 words

The memory, as set forth in claim 1, further comprising a logic circuit coupled to said switch and receiving said first acontrol signal and second control signal, an output of said logic circuit turning on said switch in response to said first control signal indicating not standby or said second control signal indicating data retention.

Claim 5

Dependent Claim 26 words

The memory, as set forth in claim 3, wherein said logic circuit includes a NOR gate receiving said first and second control signals at its input.

Claim 6

Dependent Claim 55 words

The memory, as set forth in claim 1, wherein said memory cell array is further coupled to a second supply voltage through a second switch, said second switch controllably connecting and disconnecting said memory cell array and said second supply voltage in response to selected states of said second control signal generated by said mircoporcessor.

Claim 7

Dependent Claim 21 words

The memory, as set forth in claim 5, wherein said first and second supply voltages supply the same supply voltage level.

Claim 8

Dependent Claim 20 words

The memory, as set forth in claim 5, wherein said first and second supply voltages supply different supply voltage levels.

Claim 9

Dependent Claim 50 words

The memory, as set forth in claim 5, further comprising a second logic circuit coupled to said second switch and receiving said first control signal and a second control signal, an output of said second logic circuit turning on said second switch in response to said selected state indicating standby.

Claim 10

Dependent Claim 49 words

The memory, as set forth in claim 1, further comprising: periphery circuitry coupled to said memory cell array; and a second switch coupled between said periphery circuitry and said supply voltage responsive to a selected state of said control signal and a second control signal generated by said microprocessor.

Claim 11

Dependent Claim 95 words

A memory comprising: a plurality of memory blocks; a switch coupled between at least one of said memory blocks and a supply voltage, said switch disconnecting said at least one memory block from said supply voltage in response to a selected state of a control signal; a wordline selection circuit; a plurality of global wordlines driving selected wordline selection circuits; said wordline selection circuit coupled to said plurality of global wordlines generating a plurality of block wordlines coupled to said memory blocks in response to a respective one of a plurality of block selection singals.

Claim 12

Dependent Claim 95 words

A memory comprising: a plurality of memory blocks; a switch coupled between at least one of said memory blocks and a supply voltage, said switch disconnecting said at least one memory block from said supply voltage in response to a selected state of a control signal; a wordline selection circuit; a plurality of global wordlines driving selected wordline selection circuits; said wordline selection circuit coupled to said plurality of global wordlines generating a plurality of block wordlines coupled to said memory blocks in response to a respective one of a plurality of block selection singals.

Claim 13

Dependent Claim 39 words

The memory, as set forth in claim 10, wherein each said memory block comprises: a periphery circuitry; and a switch coupled between said periphery circuitry and said supply voltage responsive to a selected state of a second control signal.

Claim 14

Dependent Claim 56 words

The memory, as set forth in claim 10, wherein each said wordline selection circuit includes: a NAND gate receiving one of said global wordlines and a respective one of said block selection signals; and an inverter coupled to an output of said NAND gate, an output of which generates a respective one of said block wordline.

Claim 15

Dependent Claim 21 words

The memory, as set forth in claim 10, wherein said switch includes a p-channel transistor being gated by said control signal.

Claim 16

Dependent Claim 87 words

A computer system, comprising: a memory device having at least one memory cell array; a microprocessor coupled to said memory device; and a switch coupled between selected ones of said at least one memory cell array and a supply voltage, said switch disconnecting selected ones of said memory cell array from said supply voltage in response to a predetermined state of standby and data retention control signals for said memory cell array determined by said microprocessor wherein said standby and data retention control signals may independently vary.

Claim 17

Dependent Claim 87 words

A computer system, comprising: a memory device having at least one memory cell array; a microprocessor coupled to said memory device; and a switch coupled between selected ones of said at least one memory cell array and a supply voltage, said switch disconnecting selected ones of said memory cell array from said supply voltage in response to a predetermined state of standby and data retention control signals for said memory cell array determined by said microprocessor wherein said standby and data retention control signals may independently vary.

Claim 18

Dependent Claim 50 words

The computer system, as set forth in claim 14, wherein said memory device further comprises: periphery circuitry; and a switch coupled between said periphery circuitry and said supply voltage, said switch disconnecting said periphery circuitry from said supply voltage in response to another predetermined state of said memory cell array.

Claim 19

Dependent Claim 71 words

The computer system, as set forth in claim 14, wherein said memory device further comprises: a plurality of memory cell arrays; dedicated periphery circuitry coupled to each of said memory cell array; and a switch coupled between each said periphery circuitry and said supply voltage, said switches connecting and disconnecting selected ones of said periphery circuitry and said supply voltage in response to the predetermined states of said memory cell arrays.

Claim 20

Dependent Claim 83 words

The computer system, as set forth in claim 14, wherein said memory device further comprises: a plurality of memory cell arrays; a bus coupled to said microprocessor and said plurality of memory cell arrays; switches controllably connecting and disconnecting a number of selected ones of said plurality of memory cell arrays and said supply voltage; and said microprocessor generating an enable address delivered to said memory cell arrays via said bus, said enable address controlling said switches in response to memory usage requirements.

Claim 21

Dependent Claim 69 words

The computer system, as set forth in claim 14, further comprising a second switch coupled between said at least one memory cell array and a second supply voltage, said memory cell array being connected to said supply voltage in response to a first predetermined state of said memory cell array, and being connected to said second supply voltage in response to another predetermined state of said memory cell array.

Claim 22

Dependent Claim 51 words

The computer system, as set forth in claim 14, further comprising a logic circuit receiving a standby control signal and a data retention control signal, an output of said logic circuit controlling said switch in response to selected states of said standby and data retention control signal generated by said microprocessor.

Claim 23

Dependent Claim 54 words

The computer system, as set forth in claim 14, further comprising a logic circuit receiving a first and second control signal, an output of said logic circuit turning on said switch in response to said first control signal indicating not standby or said second control signal indicating data retention as determined by said microprocessor.

Claim 24

Dependent Claim 57 words

The computer system, as set forth in claim 14, wherein said memory cell array includes: a plurality of memory blocks; and a switch coupled between each said memory block and said power supply, said switches disconnecting respective memory blocks from said power supply in response to a selected state of a control signal generated by said microprocessor.

Claim 25

Dependent Claim 112 words

The memory, as set forth in claim 14, wherein said memory cell array includes: a plurality of memory blocks; a switch coupled between each said memory block and said power supply, said switches disconnecting respective memory blocks from said power supply in response to selected states of a standby control signal and a data retention control signal generated by said microprocessor; a plurality of global wordlines driving selected rows of memory cells of said memory cell array; wordline selection circuits coupled to said plurality, of global wordlines generating a plurality of block wordlines coupled to respective memory blocks in response to a plurality of respective block selection signals generated by said microprocessor.

Claim 26

Independent Claim 69 words

A method for reducing power consumption and leakage current in a memory cell array in a computer system, compirising the steps of: dividing said memory cell array into a plurality of memory blocks; and determining memory use, both standby for active blocks and data retention for blocks with data to be retained, in terms of the number of memory blocks, and selectively providing power to those memory blocks needed.

Claim 27

Independent Claim 69 words

A method for reducing power consumption and leakage current in a memory cell array in a computer system, compirising the steps of: dividing said memory cell array into a plurality of memory blocks; and determining memory use, both standby for active blocks and data retention for blocks with data to be retained, in terms of the number of memory blocks, and selectively providing power to those memory blocks needed.

Claim 28

Dependent Claim 97 words

The method, as set forth in claim 23, further comprising the steps of: determining whether data retention is required for the memory blocks; generating a standby signal for each of said plurality of memory blocks indicative of an active/inactive status of said respective memory blocks; generating a data retention signal for each of said plurality of memory blocks indicative of whether data stored in said respective memory blocks are to be retained; and selectively providing power to those memory blocks having a standby signal indicating an active status, or a data retention signal indicating data retention required.

Claim 29

Dependent Claim 26 words

The method, as set forth in claim 23, further comprising the step of selectively providing power to a minimal number of memory blocks upon power up.

Claim 30

Dependent Claim 24 words

The method, as set forth in claim 23, further comprising the step of generating block wordlines for driving selected rows of selected memory blocks.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-03-24	2000-09-23	2001-03-25	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-03-24	2004-09-23	2005-03-25	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-03-24	2008-09-23	2009-03-25	$7700.00	Window Closed / Lapsed

Selective power to memory

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