US5618744A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Manufacturing method and apparatus of a semiconductor integrated circuit device
Assignee: Fujitsu VLSI Ltd
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Filing: 1993-09-22
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Granted: 1997-04-08
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Expires: 2013-09-22
Abstract
Abstract According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
Inventors
- 👤 Rieko Suzuki
- 👤 Kiyoshi Saida
- 👤 Kazushige Itazu
- 👤 Eiji Fujine
- 👤 Yoshihiro Kamiya
- 👤 Yoshitaka Uchida
- 👤 Takako Murakami
- 👤 Teruhisa Tsuyuki
- 👤 Kazunori Kawazoe
- 👤 Takeshi Shimazaki
- 👤 Yukimi Nishiwaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:25
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
142 words
A method for disposing an actual pattern of a logic cell utilizing basic cells provided on a semiconductor substrate of a semiconductor integrated circuit device, wherein each of said basic cells includes a PMOS transistor and an NMOS transistor adjacent to each other, and wherein a high power supply line and low power supply line are formed to pass over each of said basic cells, the method comprising: alternately forming said high power supply line and low power supply line so that they extend along both PMOS and NMOS transistors in each of said basic cells without overlapping said transistors; preforming said actual pattern including a plurality of wirings connected to said high power supply line and said low power supply line and internal wirings within said basic cells; and disposing said actual pattern utilizing said basic cells at a determined location.
Claim 2
Independent Claim
142 words
A method for disposing an actual pattern of a logic cell utilizing basic cells provided on a semiconductor substrate of a semiconductor integrated circuit device, wherein each of said basic cells includes a PMOS transistor and an NMOS transistor adjacent to each other, and wherein a high power supply line and low power supply line are formed to pass over each of said basic cells, the method comprising: alternately forming said high power supply line and low power supply line so that they extend along both PMOS and NMOS transistors in each of said basic cells without overlapping said transistors; preforming said actual pattern including a plurality of wirings connected to said high power supply line and said low power supply line and internal wirings within said basic cells; and disposing said actual pattern utilizing said basic cells at a determined location.
Claim 3
Dependent Claim
60 words
A method according to claim 1, wherein a plurality of actual patterns are provided for making each of said logic cells, and wherein said plurality of said wirings comprise a first wiring including a first contact hole connected to said high power supply line and a second wiring including a second contact hole connected to said low power supply line.
Claim 4
Independent Claim
273 words
A method for disposing an actual pattern of a logic cell utilizing basic cells provided on a semiconductor substrate of a semiconductor integrated circuit device, wherein each of said basic cells includes a PMOS transistor and an NMOS transistor adjacent to each other, and wherein a high power supply line and low power supply line are formed to pass over each of said basic cells, the method comprising: alternately forming said high power supply line and low power supply line so that they extend along both PMOS and NMOS transistors in each of said basic cells; performing said actual pattern including a plurality of wirings connected to said high power supply line and said low power supply line and internal wirings within said basic cells; and disposing said actual pattern utilizing said basic cells at a determined location; wherein said plurality of said wirings comprise a third wiring to be coupled to said high power supply line, extending from said high power supply line, extending from said high power supply line to said low power supply line so as to intersect with said high and low power supply lines, and a fourth wiring to be coupled to said low power supply line, extending from said high power supply line to said low power supply line so as to intersect with said high and low power supply lines, and wherein said method further includes disposing contact hole patterns at the intersection of said third line and said high power supply line and at the intersection of said fourth line and said low power supply line after disposing said actual pattern on said logic cells.
Claim 5
Independent Claim
273 words
A method for disposing an actual pattern of a logic cell utilizing basic cells provided on a semiconductor substrate of a semiconductor integrated circuit device, wherein each of said basic cells includes a PMOS transistor and an NMOS transistor adjacent to each other, and wherein a high power supply line and low power supply line are formed to pass over each of said basic cells, the method comprising: alternately forming said high power supply line and low power supply line so that they extend along both PMOS and NMOS transistors in each of said basic cells; performing said actual pattern including a plurality of wirings connected to said high power supply line and said low power supply line and internal wirings within said basic cells; and disposing said actual pattern utilizing said basic cells at a determined location; wherein said plurality of said wirings comprise a third wiring to be coupled to said high power supply line, extending from said high power supply line, extending from said high power supply line to said low power supply line so as to intersect with said high and low power supply lines, and a fourth wiring to be coupled to said low power supply line, extending from said high power supply line to said low power supply line so as to intersect with said high and low power supply lines, and wherein said method further includes disposing contact hole patterns at the intersection of said third line and said high power supply line and at the intersection of said fourth line and said low power supply line after disposing said actual pattern on said logic cells.
Claim 6
Independent Claim
291 words
A method for disposing an actual pattern of a logic cell utilizing basic cells provided on a semiconductor substrate of a semiconductor integrated circuit device, wherein each of said basic cells includes a PMOS transistor and an NMOS transistor adjacent to each other, and wherein a high power supply line and low power supply line are formed to pass over each of said basic cells, the method comprising: alternately forming said high power supply line and low power supply line so that they extend along both PMOS and NMOS transistors in each of said basic cells; preforming said actual pattern including a plurality of wirings connected to said high power supply line and said low power supply line and internal wirings within said basic cells for said logic cell; and disposing said actual pattern utilizing said basic cells at a determined location; wherein said plurality of wirings comprise a fifth wiring to be coupled to said high power supply line, extending from said high power supply line to said low power line so as to intersect with said high and low power supply lines, and a sixth wiring to be coupled to said low power supply line, extending from said high power supply line to said low power supply line so as to intersect with said high and lower power supply lines, wherein said fifth and sixth wirings have contact hole patterns which can be located at intersections between said fifth and sixth wirings and associated power supply lines, and wherein said method includes removing contact hole patterns located at said intersections of said low power supply line and said fifth wiring and of said high power supply line and said sixth wiring after disposing said pattern on said logic cells.
Claim 7
Independent Claim
291 words
A method for disposing an actual pattern of a logic cell utilizing basic cells provided on a semiconductor substrate of a semiconductor integrated circuit device, wherein each of said basic cells includes a PMOS transistor and an NMOS transistor adjacent to each other, and wherein a high power supply line and low power supply line are formed to pass over each of said basic cells, the method comprising: alternately forming said high power supply line and low power supply line so that they extend along both PMOS and NMOS transistors in each of said basic cells; preforming said actual pattern including a plurality of wirings connected to said high power supply line and said low power supply line and internal wirings within said basic cells for said logic cell; and disposing said actual pattern utilizing said basic cells at a determined location; wherein said plurality of wirings comprise a fifth wiring to be coupled to said high power supply line, extending from said high power supply line to said low power line so as to intersect with said high and low power supply lines, and a sixth wiring to be coupled to said low power supply line, extending from said high power supply line to said low power supply line so as to intersect with said high and lower power supply lines, wherein said fifth and sixth wirings have contact hole patterns which can be located at intersections between said fifth and sixth wirings and associated power supply lines, and wherein said method includes removing contact hole patterns located at said intersections of said low power supply line and said fifth wiring and of said high power supply line and said sixth wiring after disposing said pattern on said logic cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-07 | 2000-10-07 | 2001-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-07 | 2004-10-07 | 2005-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-07 | 2008-10-07 | 2009-04-08 | $7700.00 | Window Closed / Lapsed |