Method and apparatus for switching between interrupt delivery mechanisms within a multi-processor system

Claim 2

Adapted to a first interrupt circuit including a programmable interrupt controller and a first advanced programmable interrupt controller configured to transfer a first interrupt request through at least one interrupt request ("IRQ1") line, and a second interrupt circuit including a second advanced programmable interrupt controller configured to transfer a second interrupt request through at least one interrupt request ("IRQ2") line, a switching circuit comprising: a combinatorial logic unit coupled to said IRQ1 line and said IRQ2 line, said combinatorial logic unit (i) asserts said IRQ1 line if said programmable interrupt controller is needed to service said second interrupt request, and (ii) deasserts said IRQ1 line if said second interrupt request is serviceable by said second advanced programmable interrupt controller to preclude said first advanced programmable interrupt controller from servicing said second interrupt request.

Claim 3

The switching circuit according to claim 1, wherein said combinatorial logic unit is further coupled to at least one control signal line enabling said second interrupt circuit to transmit at least one control signal through said at least one control signal line to assist in controlling assertion and deassertion of said IRQ1 line.

Claim 4

The switching circuit according to claim 1, wherein said second advanced programmable interrupt controller including a mask register in which at least one mask bit is used to assert and alternatively deassert said IRQ1 line.

Claim 5

The switching circuit according to claim 1 further comprising a routing matrix element coupled between said combinatorial logic unit and said IRQ1 line, said routing matrix element receives an output signal from said combinatorial logic unit and appropriately routes said output signal to said IRQ1 line in order to assert and alternatively deassert said IRQ1 line.

Claim 6

The switching circuit according to claim 1 further comprising a routing matrix element coupled between said combinatorial logic unit and said IRQ1 line, said routing matrix element receives an output signal from said combinatorial logic unit and appropriately routes said output signal to said IRQ1 line in order to assert and alternatively deassert said IRQ1 line.

Claim 7

The switching circuit according to claim 2, wherein said combinatorial logic unit includes at least one logic gate receiving said second interrupt request and said at least one control signal.

Claim 8

Operating in cooperation with a first interrupt circuit functioning as a first interrupt delivery mechanism by transferring a first interrupt request through at least one interrupt request ("IRQ1") line and a second interrupt circuit functioning as a second interrupt delivery mechanism by transferring a second interrupt request through at least one interrupt request ("IRQ2") line, a switching circuit comprising: logic means for selectively (i) asserting said IRQ1 line upon detecting said second interrupt request if said second interrupt request requires interrupt service by the first interrupt circuit, and (ii) deasserting said IRQ1 line upon detecting said second interrupt request if said second interrupt request propagating through said IRQ2 line does not require interrupt service by said first interrupt circuit; and signaling means for controlling assertion and deassertion of said IRQ1 line, said signaling means being coupled to said logic means.

Claim 9

Operating in cooperation with a first interrupt circuit functioning as a first interrupt delivery mechanism by transferring a first interrupt request through at least one interrupt request ("IRQ1") line and a second interrupt circuit functioning as a second interrupt delivery mechanism by transferring a second interrupt request through at least one interrupt request ("IRQ2") line, a switching circuit comprising: logic means for selectively (i) asserting said IRQ1 line upon detecting said second interrupt request if said second interrupt request requires interrupt service by the first interrupt circuit, and (ii) deasserting said IRQ1 line upon detecting said second interrupt request if said second interrupt request propagating through said IRQ2 line does not require interrupt service by said first interrupt circuit; and signaling means for controlling assertion and deassertion of said IRQ1 line, said signaling means being coupled to said logic means.

Claim 10

The switching circuit according to claim 7, wherein said first interrupt circuit includes a programmable interrupt controller and an advanced programmable interrupt controller.

Claim 11

The switching circuit according to claim 8, wherein said second interrupt circuit includes at least one advanced programmable interrupt controller.

Claim 12

The switching circuit according to claim 9, wherein said logic means includes at least one logic gate receiving said second interrupt request and at least one control signal propagating through said signaling means.

Claim 13

The switching circuit according to claim 10 further comprising: routing means for receiving an output signal from said logic means and for appropriately routing said output signal to said IRQ1 line in order to assert and alternatively deassert said IRQ1 line, said routing means is coupled between said logic means and said IRQ1 line.

Claim 14

A computer system comprising: at least one processor; an interrupt bus coupled to said at least one processor; an interrupt line coupled to said at least one processor; at least a first interrupt request line; at least a second interrupt request line; a first interrupt circuit coupled to said interrupt bus and said interrupt line, said first interrupt circuit receives a first interrupt request through said first interrupt request line and either places a signal representative of said first interrupt request onto said interrupt bus or asserts said interrupt line; a second interrupt circuit coupled to said interrupt bus, said second interrupt circuit receives a second interrupt request through said second interrupt request line; and a switching circuit coupled to said first and second interrupt request lines, said switching circuit selectively (i) asserts said first interrupt request line upon detecting said second interrupt request requires interrupt service to be requested by said first interrupt circuit, and (ii) deasserts said first interrupt request line upon detecting that said second interrupt request does not require interrupt service to be requested by said first interrupt circuit.

Claim 15

A computer system comprising: at least one processor; an interrupt bus coupled to said at least one processor; an interrupt line coupled to said at least one processor; at least a first interrupt request line; at least a second interrupt request line; a first interrupt circuit coupled to said interrupt bus and said interrupt line, said first interrupt circuit receives a first interrupt request through said first interrupt request line and either places a signal representative of said first interrupt request onto said interrupt bus or asserts said interrupt line; a second interrupt circuit coupled to said interrupt bus, said second interrupt circuit receives a second interrupt request through said second interrupt request line; and a switching circuit coupled to said first and second interrupt request lines, said switching circuit selectively (i) asserts said first interrupt request line upon detecting said second interrupt request requires interrupt service to be requested by said first interrupt circuit, and (ii) deasserts said first interrupt request line upon detecting that said second interrupt request does not require interrupt service to be requested by said first interrupt circuit.

Claim 16

The computer system according to claim 12, wherein said first interrupt circuit includes a programmable interrupt controller coupled to said interrupt line.

Claim 17

The computer system according to claim 13, wherein said first interrupt circuit further includes an advanced programmable interrupt controller coupled to said interrupt bus.

Claim 18

The computer system according to claim 13, wherein said second interrupt circuit includes at least one advanced programmable interrupt controller coupled to said interrupt bus.

Claim 19

The computer system according to claim 15, wherein said switching circuit includes a combinatorial logic unit coupled to said first interrupt request line and said second interrupt request line, said combinatorial logic unit selectively asserts said first interrupt request line upon detecting said second interrupt request requires interrupt servicing exclusively by said first interrupt circuit and deasserts said first interrupt request line upon detecting said second interrupt request does not require interrupt servicing by said first interrupt circuit.

Claim 20

The computer system according to claim 16, wherein said combinatorial logic unit is further coupled to at least one control signal line propagating at least one control signal from said second interrupt circuit, said at least one control signal controls assertion and deassertion of said first interrupt request line.

Claim 21

The computer system according to claim 17, wherein said combinatorial logic unit includes at least one logic gate receiving said second interrupt request and said at least one control signal.

Claim 22

The computer system according to claim 18, further comprising a routing matrix element coupled between said combinatorial logic unit and said first interrupt request line, said routing matrix element receives an output signal from said combinatorial logic unit and appropriately routes said output signal to said first interrupt request line in order to assert and alternatively deassert said first interrupt request line.

Claim 23

A computer system comprising: processor means for servicing a plurality of interrupt requests; bus means for interrupting said process or means; line means for interrupting said processor means; first interrupt means for receiving a first interrupt request through a first interrupt request line for signaling said processor means to service said first interrupt request; second interrupt means for receiving a second interrupt request through a second interrupt request line; and switching means for selectively (i) asserting said first interrupt request line upon detecting that said second interrupt request requires interrupt service to be requested by said first interrupt means and (ii) deasserting said first interrupt request line upon detecting that said second interrupt request does not require interrupt service to be requested by said first interrupt means.

Claim 24

A computer system comprising: processor means for servicing a plurality of interrupt requests; bus means for interrupting said process or means; line means for interrupting said processor means; first interrupt means for receiving a first interrupt request through a first interrupt request line for signaling said processor means to service said first interrupt request; second interrupt means for receiving a second interrupt request through a second interrupt request line; and switching means for selectively (i) asserting said first interrupt request line upon detecting that said second interrupt request requires interrupt service to be requested by said first interrupt means and (ii) deasserting said first interrupt request line upon detecting that said second interrupt request does not require interrupt service to be requested by said first interrupt means.

Claim 25

The computer system according to claim 20, wherein said first interrupt means includes a programmable interrupt controller.

Claim 26

The computer system according to claim 21, wherein said first interrupt means further includes a programmable interrupt controller coupled to said line means.

Claim 27

The computer system according to claim 21, wherein said second interrupt means includes at least one advanced programmable interrupt controller coupled to said bus means.

Claim 28

The computer system according to claim 23, wherein said switching means includes logic means for selectively asserting and alternatively deasserting said first interrupt request line.

Claim 29

The computer system according to claim 24, wherein said logic means is further coupled to at least one control signal line propagating at least one control signal from said second interrupt means, said at least one control signal controls assertion and deassertion of said first interrupt request line.

Claim 30

The computer system according to claim 25, wherein said logic means includes at least one logic gate receiving said second interrupt request and said at least one control signal.

Claim 31

The computer system according to claim 26, further comprising a routing means, coupled between said logic means and said first interrupt request line, to receive an output signal from said logic means and appropriately route said output signal to said first interrupt request line in order to assert and alternatively deassert said first interrupt request line.

Claim 34

A computer system comprising: at least one processor; an interrupt bus coupled to said at least one processor; an interrupt line coupled to said at least one processor at least a first interrupt request line; at least a first interrupt request line; a first interrupt circuit including a programmable interrupt controller and a first advanced programmable interrupt controller configured to transfer a first interrupt request through said first interrupt request line; a second interrupt circuit including a second advanced programmable interrupt controller configured to transfer a second interrupt request through said second interrupt request line; and a switching circuit, coupled to said first interrupt request line and said second interrupt request line, including: a combinatorial logic unit, and routing matrix element coupled between said combinatorial logic unit and said first interrupt request line, said routing matrix element receives an output signal from said combinatorial logic unit and appropriately routes said output signal to assert and alternatively deassert said first interrupt request line.

Claim 35

A computer system comprising: at least one processor; an interrupt bus coupled to said at least one processor; an interrupt line coupled to said at least one processor at least a first interrupt request line; at least a first interrupt request line; a first interrupt circuit including a programmable interrupt controller and a first advanced programmable interrupt controller configured to transfer a first interrupt request through said first interrupt request line; a second interrupt circuit including a second advanced programmable interrupt controller configured to transfer a second interrupt request through said second interrupt request line; and a switching circuit, coupled to said first interrupt request line and said second interrupt request line, including: a combinatorial logic unit, and routing matrix element coupled between said combinatorial logic unit and said first interrupt request line, said routing matrix element receives an output signal from said combinatorial logic unit and appropriately routes said output signal to assert and alternatively deassert said first interrupt request line.