Method of forming silicon/silicon-germanium heterojunction bipolar transistor

Claim 1

A method for producing a low capacitance, high speed, heterojunction transistor, the method comprising the steps of: a. initially processing a p type Si substrate having a surface, including: (1) creating a n type collector region on said surface by forming an n + Si layer on said surface and depositing an n - Si layer over said n + Si layer; (2) growing a field oxide layer over said top surface and said collector region, depositing a first p + -type polycrystalline Si layer over said field oxide layer, growing a SiO 2 layer over said first p + type polycrystalline Si layer, wherein a window is defined through each of said field oxide, said first p + type polycrystalline Si and said SiO 2 layers to expose an active region of the transistor over a portion of said collector region; b. non-selectively depositing a p type SiGe layer over said field oxide layer and into said window; c. non-selectively depositing an n type Si layer over said p type SiGe layer; d. depositing a dielectric layer over said n type Si layer; e. opening at least first, second, and third contact windows through said dielectric layer, said first window defining an emitter contact window exposing said n type Si layer said second window defining a base contact exposing said p type SiGe layer, and said third contact window exposing said collector region; and f. metalizing contacts in said first, second and third windows; g. non-selectively depositing a second p type polycrystalline Si layer over said SiO 2 layer and into said active region prior to commencing step b; and h. removing said second polycrystalline Si layer of step g. from a bottom part of said window in said active region, and said second polycrystalline Si layer of step g. and said SiO 2 layer from a region overlying said first p + -type polycrystalline Si layer, prior to commencing step b.

Claim 2

A method for producing a low capacitance, high speed, heterojunction transistor, the method comprising the steps of: a. initially processing a p type Si substrate having a surface, including: (1) creating a n type collector region on said surface by forming an n + Si layer on said surface and depositing an n - Si layer over said n + Si layer; (2) growing a field oxide layer over said top surface and said collector region, depositing a first p + -type polycrystalline Si layer over said field oxide layer, growing a SiO 2 layer over said first p + type polycrystalline Si layer, wherein a window is defined through each of said field oxide, said first p + type polycrystalline Si and said SiO 2 layers to expose an active region of the transistor over a portion of said collector region; b. non-selectively depositing a p type SiGe layer over said field oxide layer and into said window; c. non-selectively depositing an n type Si layer over said p type SiGe layer; d. depositing a dielectric layer over said n type Si layer; e. opening at least first, second, and third contact windows through said dielectric layer, said first window defining an emitter contact window exposing said n type Si layer said second window defining a base contact exposing said p type SiGe layer, and said third contact window exposing said collector region; and f. metalizing contacts in said first, second and third windows; g. non-selectively depositing a second p type polycrystalline Si layer over said SiO 2 layer and into said active region prior to commencing step b; and h. removing said second polycrystalline Si layer of step g. from a bottom part of said window in said active region, and said second polycrystalline Si layer of step g. and said SiO 2 layer from a region overlying said first p + -type polycrystalline Si layer, prior to commencing step b.

Claim 5

A method for producing a low capacitance, high speed, heterojunction semiconductor device, the method comprising the steps of: a. initially processing a p-type Si substrate having a top surface, including: (1) creating a subcollector region on said top surface; (2) growing a field oxide layer over said top surface of said substrate and over said subcollector region, said field oxide layer defining a window therethrough to expose an active region of said semiconductor device; b. depositing a first silicon layer in said window; c. depositing a second silicon layer over said field oxide layer and over said first silicon layer to form an integral collector structure, wherein the part of said integral collector structure that overlies said field oxide layer has a polycrystalline structure and wherein the part of said integral collector structure that overlies said first silicon layer has an epitaxial structure; d. depositing an integral base layer of SiGe on top of said integral collector structure wherein the part of said integral base layer that overlies said polycrystalline part of said integral collector structure has a polycrystalline structure and wherein the part of said integral base layer that overlies said epitaxial part of said integral collector structure has an epitaxial structure; e. depositing third silicon layer over said SiGe base layer, wherein the part of said third silicon layer that overlies said epitaxial part of said SiGe base layer has an epitaxial structure, and any part of said third silicon layer that overlies said polycrystalline part of said SiGe base layer has a polycrystalline structure; and f. placing a heavily doped, n-type, polycrystalline-silicon emitter layer over said deposited integral base and third silicon layers.

Claim 6

A method for producing a low capacitance, high speed, heterojunction semiconductor device, the method comprising the steps of: a. initially processing a p-type Si substrate having a top surface, including: (1) creating a subcollector region on said top surface; (2) growing a field oxide layer over said top surface of said substrate and over said subcollector region, said field oxide layer defining a window therethrough to expose an active region of said semiconductor device; b. depositing a first silicon layer in said window; c. depositing a second silicon layer over said field oxide layer and over said first silicon layer to form an integral collector structure, wherein the part of said integral collector structure that overlies said field oxide layer has a polycrystalline structure and wherein the part of said integral collector structure that overlies said first silicon layer has an epitaxial structure; d. depositing an integral base layer of SiGe on top of said integral collector structure wherein the part of said integral base layer that overlies said polycrystalline part of said integral collector structure has a polycrystalline structure and wherein the part of said integral base layer that overlies said epitaxial part of said integral collector structure has an epitaxial structure; e. depositing third silicon layer over said SiGe base layer, wherein the part of said third silicon layer that overlies said epitaxial part of said SiGe base layer has an epitaxial structure, and any part of said third silicon layer that overlies said polycrystalline part of said SiGe base layer has a polycrystalline structure; and f. placing a heavily doped, n-type, polycrystalline-silicon emitter layer over said deposited integral base and third silicon layers.

Claim 11

A method for producing a low capacitance, high speed, heterojunction semiconductor device, the method comprising the steps of: a. initially processing a p-type Si substrate having a surface, including: (1) creating a subcollector region on said substrate surface; (2) growing a field oxide layer over said surface and over said subcollector region and defining a window therethrough to expose an active region of said semiconductor device; b. depositing a first silicon layer in said window; and c. growing a multilayer, epitaxial/polycrystalline structure on said surface, said epitaxial/polycrystalline structure comprising a top layer of silicon, a middle layer of Si 1-x Ge x , and a bottom layer of silicon, wherein said part of said epitaxial/polycrystalline structure overlying said oxide layer has a polycrystalline structure and wherein said part of said epitaxial/polycrystalline structure overlying said silicon layer has an epitaxial structure; and d. placing a heavily doped, n-type, polycrystalline-silicon emitter layer over the deposited base and epitaxial silicon layers; wherein said top and bottom silicon layers are n-type doped.

Claim 12

A method for producing a low capacitance, high speed, heterojunction semiconductor device, the method comprising the steps of: a. initially processing a p-type Si substrate having a surface, including: (1) creating a subcollector region on said substrate surface; (2) growing a field oxide layer over said surface and over said subcollector region and defining a window therethrough to expose an active region of said semiconductor device; b. depositing a first silicon layer in said window; and c. growing a multilayer, epitaxial/polycrystalline structure on said surface, said epitaxial/polycrystalline structure comprising a top layer of silicon, a middle layer of Si 1-x Ge x , and a bottom layer of silicon, wherein said part of said epitaxial/polycrystalline structure overlying said oxide layer has a polycrystalline structure and wherein said part of said epitaxial/polycrystalline structure overlying said silicon layer has an epitaxial structure; and d. placing a heavily doped, n-type, polycrystalline-silicon emitter layer over the deposited base and epitaxial silicon layers; wherein said top and bottom silicon layers are n-type doped.