US5633505A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor wafer incorporating marks for inspecting first layer overlay shift in global alignment process
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1996-05-20
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Granted: 1997-05-27
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Expires: 2016-05-20
Abstract
Abstract An inspection pattern on a semiconductor wafer for inspecting is used to determine the degree of alignment of a first device layer during manufacture of integrated circuits on a semiconductor substrate the following steps. Form a zeroth layer on the substrate. The alignment marks and zeroth layer mother overlay inspection patterns are patterned simultaneously in the zeroth layer aligning to alignment marks formed in the zeroth layer. Then one forms a first layer on the substrate patterned simultaneously with formation of child overlay inspection patterns patterned in the sake position as the zeroth layer mother inspection patterns to determine the overlay shift of the first layer.
Inventors
- 👤 Wen-Jye Chung
- 👤 Chu-Mei Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:47
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/277; G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70605; G03F7/70616; G03F7/70633; G03F9/00; G03F9/70; H10W; H10W46/00; H10P74/20; H10P74/203; H10W46/101; H10W46/201; H10W46/501; Y; Y10; Y10S; Y10S438/00; Y10S438/975
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
106 words
A semiconductor wafer incorporates an inspection pattern on said semiconductor wafer for inspecting to determine the degree of alignment of a first device layer during manufacture of integrated circuits on a semiconductor substrate, comprising a zeroth layer formed on said substrate patterned with global alignment marks and zeroth layer mother overlay inspection patterns formed in said zeroth layer, a first layer on said substrate patterned with child overlay inspection patterns patterned in the same position as said zeroth layer mother inspection patterns, whereby it is possible to determine the overlay shift of said first layer with said mother inspection pattern and said child overlay inspection pattern.
Claim 2
Dependent Claim
106 words
A semiconductor wafer incorporates an inspection pattern on said semiconductor wafer for inspecting to determine the degree of alignment of a first device layer during manufacture of integrated circuits on a semiconductor substrate, comprising a zeroth layer formed on said substrate patterned with global alignment marks and zeroth layer mother overlay inspection patterns formed in said zeroth layer, a first layer on said substrate patterned with child overlay inspection patterns patterned in the same position as said zeroth layer mother inspection patterns, whereby it is possible to determine the overlay shift of said first layer with said mother inspection pattern and said child overlay inspection pattern.
Claim 3
Dependent Claim
19 words
A wafer in accordance with claim 1 wherein said overlay inspection patterns are Juxtaposed with said global alignment marks.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-26 | 2000-11-25 | 2001-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-26 | 2004-11-25 | 2005-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-26 | 2008-11-25 | 2009-05-27 | $7700.00 | Window Closed / Lapsed |