Row decoder/driver circuit for determining non selected wordlines and for driving non-selected wordlines to a potential less than the lowest potential of the digit lines

Claim 2

A row decoder circuit for driving a wordline to a first potential and a second potential, wherein the second potential has a value less than a ground reference potential, and for determining which of said first and second potentials shall be driven to said wordline, the row decoder circuit comprising: a) a driver input node for receiving select and non-select signals, the wordline driven to said first potential in response to said select signal and driven to said second potential in response to said non-select signal; b) a negative node connectable to a negative potential having a value less than said ground reference potential; c) a pull-down device interposed between the wordline and said negative node and responsive to said non-select signal, wherein said second potential is driven to said wordline when said wordline is pulled toward said negative potential through said pull-down device in response to said non-select signal; and d) a latch circuit coupled to said wordline and said driver input node, said latch circuit configured to selectively latch said wordline to said second potential.

Claim 3

The row decoder circuit as specified in claim 1, wherein said first potential is an externally generated potential.

Claim 4

The row decoder circuit as specified in claim 1, wherein said first potential is a pumped potential created by internally increasing a value of an external potential.

Claim 5

The row decoder circuit as specified in claim 1, wherein said second potential on said wordline substantially eliminates a leakage current of an access device in electrical communication with said wordline.

Claim 6

The row decoder circuit as specified in claim 1, wherein said latch circuit comprises: a) a supply node connectable to a supply potential; and b) a pull-up feedback device interposed between said supply node and said driver input node and responsive to said first and said second potentials on the wordline, a potential of said driver input node pulled toward a value of said supply potential through said pull-up feedback device.

Claim 7

The row decoder circuit as specified in claim 5, further comprising an anti-latch-up device configured to substantially eliminate unwanted forward biasing of said pull-up feedback device.

Claim 8

The row decoder circuit as specified in claim 6, wherein said anti-latch-up device is interposed between said pull-up feedback device and said driver input node and connected to said supply node at a control input, said anti-latch-up device configured to substantially eliminate unwanted forward biasing of said pull-up feedback device.

Claim 9

A row decoder circuit for driving a wordline to a first potential and a second potential, wherein the second potential has a value less than a ground reference potential, and for determining which of said first and second potentials shall be driven to said wordline, the row decoder circuit comprising: a driver input node for receiving select and non-select signals, the wordline driven to said first potential in response to said select signal and driven to said second potential in response to said non-select signal; b) a negative node connectable to a negative potential having a value less than said ground reference potential; c) a pull-down device interposed between the wordline and said negative node and responsive to said non-select signal, wherein said second potential is driven to said wordline when said wordline is pulled toward said negative potential through said pull-down device in response to said non-select signal; and d) a static circuit configured to maintain said select signal at a level capable of driving said wordline to said first potential.

Claim 10

A row decoder circuit for driving a wordline to a first potential and a second potential, wherein the second potential has a value less than a ground reference potential, and for determining which of said first and second potentials shall be driven to said wordline, the row decoder circuit comprising: a driver input node for receiving select and non-select signals, the wordline driven to said first potential in response to said select signal and driven to said second potential in response to said non-select signal; b) a negative node connectable to a negative potential having a value less than said ground reference potential; c) a pull-down device interposed between the wordline and said negative node and responsive to said non-select signal, wherein said second potential is driven to said wordline when said wordline is pulled toward said negative potential through said pull-down device in response to said non-select signal; and d) a static circuit configured to maintain said select signal at a level capable of driving said wordline to said first potential.

Claim 11

The row decoder circuit as specified in claim 8, wherein said static circuit further comprises a pull-down feedback device interposed between said negative node and said driver input node and responsive to said first and said second potentials on the wordline, a potential of said driver input node pulled toward a value of said negative potential through said pull-down feedback device to perpetuate the potential at said driver input node having a same effect as said select signal.

Claim 12

The row decoder circuit as specified in claim 9, further comprising an anti-latch-up device interposed between said pull-down feed-back device and said driver input node and connected to said negative node at a control input, said anti-latch-up device configured to substantially eliminate unwanted forward biasing of said pull-down feedback device.

Claim 13

A row decoder circuit for driving a wordline to a first potential and a second potential, wherein the second potential has a value less than a ground reference potential, and for determining which of said first and second potentials shall be driven to said wordline, the row decoder circuit comprising: a) a driver input node for receiving select and non-select signals, the wordline driven to said first potential in response to said select signal and driven to said second potential in response to said non-select signal; b) a negative node connectable to a negative potential having a value less than said ground reference potential; c) a pull-down device interposed between the wordline and said negative node and responsive to said non-select signal wherein said second potential is driven to said wordline when said wordline is pulled toward said negative potential through said pull-down device in response to said non-select signal; and d) a select signal generator in electrical communication with said driver input node, said select signal generator configured to generate said select signal to have a negative potential less than the ground reference potential.

Claim 14

A row decoder circuit for driving a wordline to a first potential and a second potential, wherein the second potential has a value less than a ground reference potential, and for determining which of said first and second potentials shall be driven to said wordline, the row decoder circuit comprising: a) a driver input node for receiving select and non-select signals, the wordline driven to said first potential in response to said select signal and driven to said second potential in response to said non-select signal; b) a negative node connectable to a negative potential having a value less than said ground reference potential; c) a pull-down device interposed between the wordline and said negative node and responsive to said non-select signal wherein said second potential is driven to said wordline when said wordline is pulled toward said negative potential through said pull-down device in response to said non-select signal; and d) a select signal generator in electrical communication with said driver input node, said select signal generator configured to generate said select signal to have a negative potential less than the ground reference potential.

Claim 15

The row decoder as specified in claim 11, further comprising: a) a pass device electrically interposed between said select signal generator and said driver input node, said pass device, when actuated, passing said select and said non-select signals from an output node of said select signal generator to said driver input node, said pass device having a control input; and b) a level translator circuit in electrical communication with said control input of said pass device and configured to generate a negative potential less than a ground reference potential at said control input.

Claim 16

A circuit having a plurality of memory cells, a plurality of digit lines, and a plurality of wordlines, each one of the memory cells located at an intersection of one of the digit lines and one of the wordlines, comprising: a) a means for selecting a non-selected wordline of said plurality of wordlines, said non-selected wordline associated with a non-selected memory cell of said plurality of said memory cells; b) a means for driving a potential to the non-selected wordline which is less than a lowest potential driven to any of the digit lines of the plurality during an operation of the circuit; and c) a latch circuit configured to latch the potential to the non-selected wordline.

Claim 17

A circuit having a plurality of memory cells, a plurality of digit lines, and a plurality of wordlines, each one of the memory cells located at an intersection of one of the digit lines and one of the wordlines, comprising: a) a means for selecting a non-selected wordline of said plurality of wordlines, said non-selected wordline associated with a non-selected memory cell of said plurality of said memory cells; b) a means for driving a potential to the non-selected wordline which is less than a lowest potential driven to any of the digit lines of the plurality during an operation of the circuit; and c) a latch circuit configured to latch the potential to the non-selected wordline.

Claim 20

A module, comprising: a) a plurality of address nodes; b) at least one integrated circuit connected to said plurality of address nodes, said integrated circuit comprising i) a plurality of memory cells for storing data; ii) a plurality of digit lines for accepting the data; iii) a plurality of wordlines, each one of said memory cells located at an intersection of one of said digit lines and one of said wordlines; and iv) a decode means for selecting a non-selected wordline of said plurality of wordlines in response to an address on said plurality of address nodes, said non-selected wordline associated with a non-selected memory cell of said plurality of said memory cells; c) a driver means for driving a potential to the non-selected wordline which is less than a lowest potential driven to any of the digit lines of the plurality during an operation of the at least one integrated circuit; and d) a latch circuit configured to latch the potential to the non-selected wordline.

Claim 21

A module, comprising: a) a plurality of address nodes; b) at least one integrated circuit connected to said plurality of address nodes, said integrated circuit comprising i) a plurality of memory cells for storing data; ii) a plurality of digit lines for accepting the data; iii) a plurality of wordlines, each one of said memory cells located at an intersection of one of said digit lines and one of said wordlines; and iv) a decode means for selecting a non-selected wordline of said plurality of wordlines in response to an address on said plurality of address nodes, said non-selected wordline associated with a non-selected memory cell of said plurality of said memory cells; c) a driver means for driving a potential to the non-selected wordline which is less than a lowest potential driven to any of the digit lines of the plurality during an operation of the at least one integrated circuit; and d) a latch circuit configured to latch the potential to the non-selected wordline.