Method of isolating active areas of a semiconductor substrate by shallow trenches and narrow trenches

Claim 2

Method of isolating active areas of a semiconductor substrate with lateral trenches, comprising: a) trenches are formed in the semiconductor substrate laterally of first regions of the substrate which subsequently form said active areas, b) a layered structure is deposited in the trenches and on said first regions of the substrate, comprising a layer of a planarising insulative first oxide between two layers of a conformal second oxide to form a semiconductor block, c) the semiconductor block formed in step b) is annealed, and d) the annealed semiconductor block is planarised to uncover the upper surface of said first regions of the substrate and to leave in the trenches the conformal oxide and the planarising oxide.

Claim 3

Method of isolating active areas of a semiconductor substrate with lateral trenches, comprising: a) trenches are formed in the semiconductor substrate laterally of first regions of the substrate which subsequently form said active areas, b) a layered structure is deposited in the trenches and on said first regions of the substrate, comprising a layer of a planarising insulative first oxide between two layers of a conformal second oxide to form a semiconductor block, c) the semiconductor block formed in step b) is annealed, and d) the annealed semiconductor block is planarised to uncover the upper surface of said first regions of the substrate and to leave in the trenches the conformal oxide and the planarising oxide, wherein said trenches have a lateral dimension (L) and a depth (P) and in step b), to form said layered structure, there are deposited a first conformal oxide layer having a thickness chosen according to the minimal lateral dimension (L) of the trenches, then the planarising insulative first oxide layer having a thickness chosen to obtain a relief variation less than a first threshold for the trenches of minimal lateral dimension, and finally a second conformal oxide layer having a thickness chosen according to the depth (P) of the trench.

Claim 4

Method of isolating active areas of a semiconductor substrate with lateral trenches, comprising: a) trenches are formed in the semiconductor substrate laterally of first regions of the substrate which subsequently form said active areas, b) a layered structure is deposited in the trenches and on said first regions of the substrate, comprising a layer of a planarising insulative first oxide between two layers of a conformal second oxide to form a semiconductor block, c) the semiconductor block formed in step b) is annealed, and d) the annealed semiconductor block is planarised to uncover the upper surface of said first regions of the substrate and to leave in the trenches the conformal oxide and the planarising oxide, wherein said trenches have a lateral dimension (L) and a depth (P) and in step b), to form said layered structure, there are deposited a first conformal oxide layer having a thickness chosen according to the minimal lateral dimension (L) of the trenches, then the planarising insulative first oxide layer having a thickness chosen to obtain a relief variation less than a first threshold for the trenches of minimal lateral dimension, and finally a second conformal oxide layer having a thickness chosen according to the depth (P) of the trench.

Claim 5

Method according to claim 2 wherein the thickness of the first conformal oxide layer is between 1/4 and 1/3 the minimal lateral dimension (L) of the trenches and said first threshold is in the order of 200 Å.

Claim 6

Method according to claim 2 wherein the thickness of the planarising insulative first oxide layer is between 1000 Å and 2000 Å.

Claim 7

Method according to claim 2 wherein in step a), before forming the trenches, an auxiliary layer is deposited on an insulative primary layer and the thickness of the second conformal oxide layer of the layered structure is greater than the sum of the thickness of said auxiliary layer and of the trench depth (P).

Claim 8

Method according to claim 2 wherein the planarising step d) further comprises: d1) the annealed semiconductor block is partially and selectively etched to leave on either side of each first region of the substrate or on either side of groups of neighbouring second regions of substrate projecting areas of conformal oxide, d2) a second conformal oxide layer of the semiconductor block formed in step d1) is partially mechanically/chemically polished to reduce a height of the substrate projecting areas of conformal oxide below a chosen residual relief height, d3) the first and second regions of the substrate are uncovered by chemical etching with detection of end of attack on the semiconductor block formed in step d2).

Claim 9

Method according to claim 6 wherein in step a) the definition of the first regions of the substrate includes the production of a mask and some of the substrate projecting areas are produced using a mask corresponding to the negative of the mask defining the first regions of the substrate.

Claim 10

Method according to claim 6 wherein in step a) the definition of the second regions of the substrate includes the production of a mask and some of the substrate projecting areas are produced using a mask enlarged relative to the negative of the mask defining the second regions of the substrate.

Claim 11

Method according to claim 6 wherein the residual relief height is in the order of 1000 Å.

Claim 12

Method according to claim 6 wherein end of attack is detected on the auxiliary layer serving as a barrier layer for an etching operation.

Claim 13

Method according to claim 10 wherein the chemical etching with end of attack detection is plasma etching.

Claim 14

Method according to claim 5 wherein step a) further comprises the formation on the semiconductor substrate of a primary oxide layer before deposition of the auxiliary oxide layer and in that in step d) the auxiliary oxide layer and the primary oxide layer are removed after chemical etching.

Claim 15

Method according to claim 6 wherein the annealing is effected at a temperature in the order of 1050° C.

Claim 16

Method according to claim 2 wherein some of the trenches formed have a lateral dimension between 0.2 μm and 0.5 μm and a depth/lateral dimension ratio in the order of 1.