US5644515A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hardware logic emulation system capable of probing internal nodes in a circuit design undergoing emulation
Assignee: Cadence Design Systems Inc
•
Filing: 1995-06-07
•
Granted: 1997-07-01
•
Expires: 2015-06-07
Abstract
Abstract A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. A network or internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.
Inventors
- 👤 Stephen P. Sample
- 👤 Michael R. D'Amour
- 👤 Thomas S. Payne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:22
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
227 words
A apparatus which can be configured with a circuit design in response to the input of circuit information and which transmits signal information between the configured circuit design and an external system adapted for use with a component incorporating the circuit design, said apparatus comprising: a plurality of fixed electrical conductors; a plurality of reprogrammable logic chips, each of said plurality of reprogrammable logic chips comprising input/output terminals, at least some of said input/output terminals of said plurality of reprogrammable logic chips connected to said fixed electrical conductors, said plurality of reprogrammable logic chips further comprising reprogrammable functional logic elements capable of being connected to at least some of said input/output terminals; an input/output bus; and a plurality of reconfigurable probe chips, each of said reconfigurable probe chips comprising input/output terminals, a first group of said input/output terminals of said plurality of reconfigurable probe chips connected to said input/output bus, a second group of said input/output terminals of said plurality of reconfigurable probe chips connected to said fixed electrical conductors, said fixed electrical conductors placing said second group of said input/output terminals of said plurality of reconfigurable probe chips in electrical communication with at least some of said input/output terminals of said plurality of reprogrammable logic chips, said reconfigurable probe chips transferring state information from a node within said reprogrammable functional logic elements onto said input/output bus.
Claim 2
Independent Claim
227 words
A apparatus which can be configured with a circuit design in response to the input of circuit information and which transmits signal information between the configured circuit design and an external system adapted for use with a component incorporating the circuit design, said apparatus comprising: a plurality of fixed electrical conductors; a plurality of reprogrammable logic chips, each of said plurality of reprogrammable logic chips comprising input/output terminals, at least some of said input/output terminals of said plurality of reprogrammable logic chips connected to said fixed electrical conductors, said plurality of reprogrammable logic chips further comprising reprogrammable functional logic elements capable of being connected to at least some of said input/output terminals; an input/output bus; and a plurality of reconfigurable probe chips, each of said reconfigurable probe chips comprising input/output terminals, a first group of said input/output terminals of said plurality of reconfigurable probe chips connected to said input/output bus, a second group of said input/output terminals of said plurality of reconfigurable probe chips connected to said fixed electrical conductors, said fixed electrical conductors placing said second group of said input/output terminals of said plurality of reconfigurable probe chips in electrical communication with at least some of said input/output terminals of said plurality of reprogrammable logic chips, said reconfigurable probe chips transferring state information from a node within said reprogrammable functional logic elements onto said input/output bus.
Claim 3
Dependent Claim
17 words
The apparatus of claim 1 wherein said plurality of reprogrammable logic chips comprise field programmable gate arrays.
Claim 4
Dependent Claim
17 words
The apparatus of claim 1 wherein said plurality of reconfigurable probe chips comprise field programmable gate arrays.
Claim 5
Dependent Claim
24 words
The apparatus of claim 1 wherein said plurality of reprogrammable logic chips and said plurality of reconfigurable probe chips comprise field programmable gate arrays.
Claim 6
Dependent Claim
308 words
A hardware logic emulation apparatus comprising: a plurality of fixed electrical conductors; an array of reprogrammable chips comprising a first column of reprogrammable chips and a second column of reprogrammable chips, each of said reprogrammable chips comprising input/output terminals, at least some of said input/output terminals of said reprogrammable chips connected to said fixed electrical conductors, at least some of said reprogrammable chips further comprising reprogrammable functional logic elements capable of being connected to at least some of said input/output terminals; an input/output bus; a first reconfigurable probe chip, said first reconfigurable probe chip comprising input/output terminals, a first group of said input/output terminals of said first reconfigurable probe chip connected to said input/output bus, a second group of said input/output terminals of said first reconfigurable probe chip connected to said fixed electrical conductors, said fixed electrical conductors placing said second group of said input/output terminals of said first reconfigurable probe chip in electrical communication with at least one of said input/output terminals of said reprogrammable chips in said first column, said first reconfigurable probe chip transferring state information from a node of said reprogrammable functional logic elements in said reprogrammable chips in said first column onto said input/output bus a second reconfigurable probe chip, said second reconfigurable probe chip comprising input/output terminals, a first group of said input/output terminals of said second reconfigurable probe chip connected to said input/output bus, a second group of said input/output terminals of said second reconfigurable probe chip connected to said fixed electrical conductors, said fixed electrical conductors placing said second group of said input/output terminals of said second reconfigurable probe chip in electrical communication with at least one of said input/output terminals of said reprogrammable chips in said second column; and said reconfigurable probe chips transferring state information from a node of said reprogrammable functional logic elements onto said input/output bus.
Claim 7
Dependent Claim
308 words
A hardware logic emulation apparatus comprising: a plurality of fixed electrical conductors; an array of reprogrammable chips comprising a first column of reprogrammable chips and a second column of reprogrammable chips, each of said reprogrammable chips comprising input/output terminals, at least some of said input/output terminals of said reprogrammable chips connected to said fixed electrical conductors, at least some of said reprogrammable chips further comprising reprogrammable functional logic elements capable of being connected to at least some of said input/output terminals; an input/output bus; a first reconfigurable probe chip, said first reconfigurable probe chip comprising input/output terminals, a first group of said input/output terminals of said first reconfigurable probe chip connected to said input/output bus, a second group of said input/output terminals of said first reconfigurable probe chip connected to said fixed electrical conductors, said fixed electrical conductors placing said second group of said input/output terminals of said first reconfigurable probe chip in electrical communication with at least one of said input/output terminals of said reprogrammable chips in said first column, said first reconfigurable probe chip transferring state information from a node of said reprogrammable functional logic elements in said reprogrammable chips in said first column onto said input/output bus a second reconfigurable probe chip, said second reconfigurable probe chip comprising input/output terminals, a first group of said input/output terminals of said second reconfigurable probe chip connected to said input/output bus, a second group of said input/output terminals of said second reconfigurable probe chip connected to said fixed electrical conductors, said fixed electrical conductors placing said second group of said input/output terminals of said second reconfigurable probe chip in electrical communication with at least one of said input/output terminals of said reprogrammable chips in said second column; and said reconfigurable probe chips transferring state information from a node of said reprogrammable functional logic elements onto said input/output bus.
Claim 8
Dependent Claim
225 words
An electrically reconfigurable hardware emulation apparatus which can be configured with a circuit design in response to the input of circuit information and which transmits signal information between the configured circuit design and an external system adapted or use with a component incorporating the circuit design, said electrically reconfigurable hardware emulation apparatus comprising: a plurality of fixed electrical conductors; a plurality of first field programmable gate arrays, said first field programmable gate arrays comprising input/output terminals connected to said fixed electrical conductors and reprogrammable functional logic elements capable of being connected to at least some of said input/output terminals; a plurality of second field programmable gate arrays, said second field programmable gate arrays comprising input/output terminals connected to said fixed electrical conductors and reprogrammable electrical conductors connected to at least some of said input/output terminals for reconfigurably interconnecting selected functional logic elements in one of said first field programmable gate arrays to selected functional logic elements in another of said first field programmable gate arrays containing functional logic elements; an input/output bus; and a third field programmable gate array, said third field programmable gate array comprising input/output terminals connected to said fixed electrical conductors and reprogrammable electrical conductors connected to at least some of said input/output terminals for reconfigurably interconnecting selected nodes in one of said first field programmable gate arrays to said input/output bus.
Claim 9
Dependent Claim
225 words
An electrically reconfigurable hardware emulation apparatus which can be configured with a circuit design in response to the input of circuit information and which transmits signal information between the configured circuit design and an external system adapted or use with a component incorporating the circuit design, said electrically reconfigurable hardware emulation apparatus comprising: a plurality of fixed electrical conductors; a plurality of first field programmable gate arrays, said first field programmable gate arrays comprising input/output terminals connected to said fixed electrical conductors and reprogrammable functional logic elements capable of being connected to at least some of said input/output terminals; a plurality of second field programmable gate arrays, said second field programmable gate arrays comprising input/output terminals connected to said fixed electrical conductors and reprogrammable electrical conductors connected to at least some of said input/output terminals for reconfigurably interconnecting selected functional logic elements in one of said first field programmable gate arrays to selected functional logic elements in another of said first field programmable gate arrays containing functional logic elements; an input/output bus; and a third field programmable gate array, said third field programmable gate array comprising input/output terminals connected to said fixed electrical conductors and reprogrammable electrical conductors connected to at least some of said input/output terminals for reconfigurably interconnecting selected nodes in one of said first field programmable gate arrays to said input/output bus.
Claim 10
Dependent Claim
193 words
An electrically reconfigurable hardware emulation apparatus which can be configured with a circuit design in response to the input of circuit information and which transmits signal information between the configured circuit design and an external system adapted for use with a component incorporating the circuit design, said electrically reconfigurable hardware emulation apparatus comprising: a plurality of electrically reconfigurable devices, at least some of said electrically reconfigurable devices having reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements, said electrically reconfigurable devices having reprogrammable functional logic elements further comprising nodes capable of being connected to a probe terminal; at least one other of said electrically reconfigurable devices containing reprogrammable electrical conductors which are used to reconfigurably interconnect selected input/output terminals of selected of said electrically reconfigurable devices having functional logic elements such that selected functional logic elements in one of said selected electrically reconfigurable devices having functional logic elements can be electrically coupled to selected functional logic elements in another of said selected electrically reconfigurable devices having functional logic elements; and a probe for muting signals from said probe terminal to a bus.
Claim 11
Dependent Claim
193 words
An electrically reconfigurable hardware emulation apparatus which can be configured with a circuit design in response to the input of circuit information and which transmits signal information between the configured circuit design and an external system adapted for use with a component incorporating the circuit design, said electrically reconfigurable hardware emulation apparatus comprising: a plurality of electrically reconfigurable devices, at least some of said electrically reconfigurable devices having reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements, said electrically reconfigurable devices having reprogrammable functional logic elements further comprising nodes capable of being connected to a probe terminal; at least one other of said electrically reconfigurable devices containing reprogrammable electrical conductors which are used to reconfigurably interconnect selected input/output terminals of selected of said electrically reconfigurable devices having functional logic elements such that selected functional logic elements in one of said selected electrically reconfigurable devices having functional logic elements can be electrically coupled to selected functional logic elements in another of said selected electrically reconfigurable devices having functional logic elements; and a probe for muting signals from said probe terminal to a bus.
Claim 12
Dependent Claim
68 words
The apparatus of claim 7 wherein said probe comprises at least one probe electrically reconfigurable device, said probe electrically reconfigurable device containing reprogrammable electrical conductors which are used to reconfigurably interconnect said nodes of selected of said electrically reconfigurable devices having functional logic elements such that selected nodes in one of said selected electrically reconfigurable devices having functional logic elements can be electrically coupled to said input/output bus.
Claim 13
Dependent Claim
33 words
The apparatus of claim 7 wherein said apparatus further comprises a plurality of fixed electrical conductors, at least one of said plurality of fixed electrical conductors in electrical communication with said probe terminal.
Claim 14
Dependent Claim
68 words
The apparatus of claim 9 wherein said probe comprises at least one probe electrically reconfigurable device, said probe electrically reconfigurable device containing reprogrammable electrical conductors which are used to reconfigurably interconnect said fixed electrical conductors in electrical communication with said probe terminal of selected of said electrically reconfigurable devices having functional logic elements such that signals at said probe terminal can be electrically coupled to said input/output bus.
Claim 15
Dependent Claim
232 words
An electrically reconfigurable hardware emulation apparatus which can be configured with a circuit design in response to the input of circuit information and which transmits signal information between the configured circuit design and an external system adapted or use with a component incorporating the circuit design, said electrically reconfigurable hardware emulation apparatus comprising: a plurality of fixed electrical conductors; an input/output bus; a plurality of field programmable gate arrays, at least some of said field programmable gate arrays having reprogrammable functional logic elements, said field programmable gate arrays having reprogrammable functional logic elements comprising nodes and a probe terminal connected to said fixed electrical conductors, said probe terminal capable of being connected to said nodes; at least one other of said field programmable gate arrays containing reprogrammable electrical conductors connected to at least some of said fixed electrical conductors for reconfigurably interconnecting selected functional logic elements in one of said field programmable gate arrays having functional logic elements to selected functional logic elements in another of said field programmable gate arrays having functional logic elements; and at least one other of said field programmable gate arrays containing reprogrammable electrical conductors which are used to reconfigurably interconnect said fixed electrical conductors in electrical communication with said probe terminal of said field programmable gate arrays having functional logic elements such that signals at said probe terminal can be electrically coupled to said input/output bus.
Claim 16
Dependent Claim
232 words
An electrically reconfigurable hardware emulation apparatus which can be configured with a circuit design in response to the input of circuit information and which transmits signal information between the configured circuit design and an external system adapted or use with a component incorporating the circuit design, said electrically reconfigurable hardware emulation apparatus comprising: a plurality of fixed electrical conductors; an input/output bus; a plurality of field programmable gate arrays, at least some of said field programmable gate arrays having reprogrammable functional logic elements, said field programmable gate arrays having reprogrammable functional logic elements comprising nodes and a probe terminal connected to said fixed electrical conductors, said probe terminal capable of being connected to said nodes; at least one other of said field programmable gate arrays containing reprogrammable electrical conductors connected to at least some of said fixed electrical conductors for reconfigurably interconnecting selected functional logic elements in one of said field programmable gate arrays having functional logic elements to selected functional logic elements in another of said field programmable gate arrays having functional logic elements; and at least one other of said field programmable gate arrays containing reprogrammable electrical conductors which are used to reconfigurably interconnect said fixed electrical conductors in electrical communication with said probe terminal of said field programmable gate arrays having functional logic elements such that signals at said probe terminal can be electrically coupled to said input/output bus.
References Cited (Backward Citations)
US3106698A
Cited
US3287703A
Cited
US3287702A
Cited
US3473160A
Cited
GB1444084A
Cited
US3928730A
Cited
US4020469A
Cited
US4032899A
Cited
US4306286A
Cited
US4357678A
Cited
US4386403A
Cited
US4365294A
Cited
US4459694A
Cited
US4404635A
Cited
US4510602A
Cited
US4488354A
Cited
US4503386A
Cited
JPS58205870A
Cited
US4656580A
Cited
US4525789A
Cited
US4541071A
Cited
US4539564A
Cited
US4613940A
Cited
US4527115A
Cited
US4578761A
Cited
US4791602A
Cited
US4612618A
Cited
US4621339A
Cited
US4593363A
Cited
US4577276A
Cited
US4600846A
Cited
US4675832A
Cited
US4656592A
Cited
US4870302A
Cited
US4695999A
Cited
US4949275A
Cited
US4782440A
Cited
US4642487A
Cited
US4713557A
Cited
US4695740A
Cited
US5023775A
Cited
US4706216A
Cited
US4758985A
Cited
US4697241A
Cited
US4752887A
Cited
US4766569A
Cited
US4761768A
Cited
US4864165A
Cited
US4747102A
Cited
US4674089A
Cited
US4942536A
Cited
US4740919A
Cited
GB2180382B
Cited
US4935734A
Cited
US4725835A
Cited
US4882690A
Cited
US4803636A
Cited
US4722084A
Cited
US4845633A
Cited
US4700187A
Cited
US4918594A
Cited
US4835705A
Cited
US4744084A
Cited
US4823276A
Cited
US4862347A
Cited
US4777606A
Cited
US4787061A
Cited
US4758745A
Cited
US4873459B1
Cited
US4758745B1
Cited
US4873459A
Cited
US5083083A
Cited
US4945503A
Cited
US4768196A
Cited
US4918440A
Cited
US4811214A
Cited
US4786904A
Cited
US4682440A
Cited
US4849928A
Cited
US4942615A
Cited
US4924429A
Cited
US4827427A
Cited
US4965739A
Cited
US4908772A
Cited
US4815003A
Cited
US4849904A
Cited
US5093920A
Cited
US4972372A
Cited
US4951220A
Cited
US4855669A
Cited
US4901260A
Cited
US4876466A
Cited
US4958324A
Cited
US5046017A
Cited
US4922432A
Cited
US4931946A
Cited
US5253363A
Cited
US4914612A
Cited
US5003487A
Cited
US4901259A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-30 | 2000-12-30 | 2001-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-30 | 2004-12-30 | 2005-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-30 | 2008-12-30 | 2009-07-01 | $7700.00 | Window Closed / Lapsed |