US5646878A
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Content addressable memory system
Assignee: Motorola Solutions Inc
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Filing: 1995-06-02
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Granted: 1997-07-08
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Expires: 2015-06-02
Abstract
Abstract A CAM system (2) stores a plurality of data sets in a plurality of pairs of CAM cells (4) and RAM cells (6). The portion of a particular data set stored in one of the RAM cells is accessed by inputting a tag to CAM cells that matches the portion of the data set stored in the CAM cell associated with the particular RAM cell. CAM system incorporates a novel two-stage matchline re-coding scheme to improve performance. Each of a plurality of first stage circuits (10) receives a plurality of matchline signals from a plurality of CAM sets and a plurality of data inputs from the corresponding RAM sets. Each output of the first stage circuits is further processed by a second stage circuit (12) which generates the final data output. The CAM system avoids the use of self-timed control signals and sense amplifiers.
Inventors
- 👤 Nicholas G. Samra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:45
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
404 words
A content addressable memory system comprising: a first plurality of content addressable memory (CAM) sets, each one of the first plurality of CAM sets comprising a CAM bit cell, each one of the first plurality of CAM sets generating a differing one of a first plurality of matchline signals; a first plurality of memory sets, each one of the first plurality of memory sets generating a differing one of a first plurality of data bits, each one of the first plurality of memory sets associated with a differing one of the first plurality of CAM sets; a first-first stage circuit, the first-first stage circuit receiving the first plurality of data bits and the first plurality of matchline signals, the first-first stage circuit outputting a first logic value if none of the first plurality of matchline signals is representative of a CAM match, the first-first stage circuit outputting a second logic value representative of one of the first plurality of data bits if one of the first plurality of matchline signals is representative of a CAM match; a second plurality of content addressable memory (CAM) sets, each one of the second plurality of CAM sets comprising a CAM bit cell, each one of the second plurality of CAM sets generating a differing one of a second plurality of matchline signals; a second plurality of memory sets, each one of the second plurality of memory sets generating a differing one of a second plurality of data bits, each one of the second plurality of memory sets associated with a differing one of the second plurality of CAM sets; a second-first stage circuit, the second-first stage circuit receiving the second plurality of data bits and the second plurality of matchline signals, the second-first stage circuit outputting the first logic value if none of the second plurality of matchline signals is representative of a CAM match, the second first stage circuit outputting a third logic value representative of one of the second plurality of data bits if one of the second plurality of matchline signals is representative of a CAM match; and a second stage circuit coupled to the first- and second-first stage circuits, the second stage circuit outputting a fourth logic state if both the first and second-first stage circuits output the first logic state, otherwise, the second stage circuit outputting one of either the first plurality of data bits or the second plurality of data bits.
Claim 2
Dependent Claim
404 words
A content addressable memory system comprising: a first plurality of content addressable memory (CAM) sets, each one of the first plurality of CAM sets comprising a CAM bit cell, each one of the first plurality of CAM sets generating a differing one of a first plurality of matchline signals; a first plurality of memory sets, each one of the first plurality of memory sets generating a differing one of a first plurality of data bits, each one of the first plurality of memory sets associated with a differing one of the first plurality of CAM sets; a first-first stage circuit, the first-first stage circuit receiving the first plurality of data bits and the first plurality of matchline signals, the first-first stage circuit outputting a first logic value if none of the first plurality of matchline signals is representative of a CAM match, the first-first stage circuit outputting a second logic value representative of one of the first plurality of data bits if one of the first plurality of matchline signals is representative of a CAM match; a second plurality of content addressable memory (CAM) sets, each one of the second plurality of CAM sets comprising a CAM bit cell, each one of the second plurality of CAM sets generating a differing one of a second plurality of matchline signals; a second plurality of memory sets, each one of the second plurality of memory sets generating a differing one of a second plurality of data bits, each one of the second plurality of memory sets associated with a differing one of the second plurality of CAM sets; a second-first stage circuit, the second-first stage circuit receiving the second plurality of data bits and the second plurality of matchline signals, the second-first stage circuit outputting the first logic value if none of the second plurality of matchline signals is representative of a CAM match, the second first stage circuit outputting a third logic value representative of one of the second plurality of data bits if one of the second plurality of matchline signals is representative of a CAM match; and a second stage circuit coupled to the first- and second-first stage circuits, the second stage circuit outputting a fourth logic state if both the first and second-first stage circuits output the first logic state, otherwise, the second stage circuit outputting one of either the first plurality of data bits or the second plurality of data bits.
Claim 3
Dependent Claim
85 words
The content addressable memory system of claim 1 wherein the first-first stage circuit and the second-first stage circuit each further comprise: an intermediate output node; and a plurality of pairs of transistors coupled in series between the intermediate output node and a voltage supply, each one of the plurality of pairs of transistors comprising a first and a second transistor coupled in parallel, a control electrode of the first transistor receiving a matchline signal, a control electrode of the second transistor receiving a data bit.
Claim 4
Dependent Claim
60 words
The content addressable memory system of claim 2 wherein the second stage circuit comprises: a final output node; and a plurality of transistors coupled in series between the final output node and the voltage supply, a control electrode of each one of the plurality of transistors coupled to an output of the first-first stage circuit or the second-first stage circuit.
Claim 5
Dependent Claim
45 words
The content addressable memory system of claim 3 wherein the plurality of transistors coupled in series further comprises a plurality of logic gates, each one of the plurality of logic gates coupled to the control electrode of a differing one of the plurality of transistors.
Claim 6
Dependent Claim
239 words
A content addressable memory system comprising: J*K data pairs, where J and K are integers greater than or equal to two, each of the J*K data pairs comprising: a content addressable memory (CAM) portion storing a tag and asserting a matchline signal if an input tag is logically equivalent to the tag; a memory portion storing a data word; K first stage circuits, each one of the K first stage circuits receiving J matchline signals and J data words, each one of the K first stage circuits outputting either a first voltage level or a first signal representative of one of the J data words responsive to the J matchline signals, each one of the K first stage circuits further comprising: an intermediate output node; a plurality of pairs of transistors coupled in series between the intermediate output node and a voltage supply, each one of the plurality of pairs of transistors comprising a first and a second transistor coupled in parallel, a control electrode of the first transistor receiving one of the J matchline signals, a control electrode of the second transistor receiving a data bit of one of the J*K data words; and a second stage circuit receiving K outputs of the K first stage circuits, the second stage circuit outputting a second voltage level or a second signal representative of one of the J data words responsive to K outputs of the K first stage circuits.
Claim 7
Dependent Claim
239 words
A content addressable memory system comprising: J*K data pairs, where J and K are integers greater than or equal to two, each of the J*K data pairs comprising: a content addressable memory (CAM) portion storing a tag and asserting a matchline signal if an input tag is logically equivalent to the tag; a memory portion storing a data word; K first stage circuits, each one of the K first stage circuits receiving J matchline signals and J data words, each one of the K first stage circuits outputting either a first voltage level or a first signal representative of one of the J data words responsive to the J matchline signals, each one of the K first stage circuits further comprising: an intermediate output node; a plurality of pairs of transistors coupled in series between the intermediate output node and a voltage supply, each one of the plurality of pairs of transistors comprising a first and a second transistor coupled in parallel, a control electrode of the first transistor receiving one of the J matchline signals, a control electrode of the second transistor receiving a data bit of one of the J*K data words; and a second stage circuit receiving K outputs of the K first stage circuits, the second stage circuit outputting a second voltage level or a second signal representative of one of the J data words responsive to K outputs of the K first stage circuits.
Claim 8
Dependent Claim
82 words
The content addressable memory system of claim 5 wherein the second stage circuit comprises a plurality of second stage bit cell circuits, wherein each one of the plurality of second stage bit cell circuits comprises: a final output node; and a plurality of transistors coupled in series between the final output node and the voltage supply, a control electrode of each one of the plurality of transistors coupled to an output of one of the plurality of first stage bit cell circuits.
Claim 9
Dependent Claim
45 words
The content addressable memory system of claim 6 wherein the plurality of transistors coupled in series further comprises a plurality of logic gates, each one of the plurality of logic gates coupled to the control electrode of a differing one of the plurality of transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-07 | 2001-01-06 | 2001-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-07 | 2005-01-06 | 2005-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-07 | 2009-01-06 | 2009-07-08 | $7700.00 | Window Closed / Lapsed |