US5649166A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dominator selection method for reducing power consumption in a circuit
Assignee: Cadence Design Systems Inc
•
Filing: 1995-04-24
•
Granted: 1997-07-15
•
Expires: 2015-04-24
Abstract
Abstract A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, includes the steps of: determining a dominator edge and dominated gates in the circuit, the dominated gates coupled to the first primary input lead and to edges of the plurality of edges dominated by the dominator edge; providing a dominator selector circuit to the circuit; coupling the dominator selector circuit to the dominator edge and to the first primary input lead; uncoupling the dominated gates from the first primary input lead; and coupling the dominated gates to the dominator selector circuit.
Inventors
- 👤 Alexander Saldanha
- 👤 Patrick McGeer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 16:20
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327; G06F2119/00; G06F2119/06
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
114 words
A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the method comprising the steps of: determining a dominator edge and dominated gates in the circuit, the dominated gates coupled to the first primary input lead and to edges of the plurality of edges dominated by the dominator edge; providing a dominator selector circuit to the circuit; coupling the dominator selector circuit to the dominator edge and to the first primary input lead; uncoupling the dominated gates from the first primary input lead; and coupling the dominated gates to the dominator selector circuit.
Claim 2
Independent Claim
114 words
A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the method comprising the steps of: determining a dominator edge and dominated gates in the circuit, the dominated gates coupled to the first primary input lead and to edges of the plurality of edges dominated by the dominator edge; providing a dominator selector circuit to the circuit; coupling the dominator selector circuit to the dominator edge and to the first primary input lead; uncoupling the dominated gates from the first primary input lead; and coupling the dominated gates to the dominator selector circuit.
Claim 3
Dependent Claim
159 words
The method of claim 1, wherein the dominated gates each have at least a first input and a second input, the first inputs of the dominated gates coupled to the first primary input lead, the second inputs of the dominated gates coupled to edges of the plurality of edges dominated by the dominator edge; wherein the dominator selector circuit has at least a first and a second input and an output; wherein the step of coupling the dominator selector circuit comprises the steps of: coupling the first input of the dominator selector circuit to the dominator edge; and coupling the second input of the dominator selector circuit to the first primary input lead; wherein the step of uncoupling comprises uncoupling the first inputs of the dominated gates from the first primary input lead; and wherein the step of coupling the dominated gates comprises coupling the first inputs of the dominated gates to the output of the dominator selector circuit.
Claim 4
Dependent Claim
14 words
The method of claim 1 wherein, the dominator selector circuit is an AND gate.
Claim 5
Dependent Claim
11 words
A circuit produced in accordance with the process of claim 1.
Claim 6
Dependent Claim
45 words
The method of claim 1, wherein the step of determining a dominator edge and dominated gates comprises the steps of: determining a dominator set of edges and the set of dominated gates; and determining the dominator edge in response to the dominator set of edges.
Claim 7
Dependent Claim
27 words
The method of claim 5, wherein the step of determining the dominator edge in response to the dominator set comprises ORing the dominator set of edges together.
Claim 8
Independent Claim
270 words
A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the method comprising the steps of: determining a first dominator edge and a first set of dominated gates in the circuit, the first set of dominated gates coupled to the first primary input lead and to a first set edges of the plurality of edges dominated by the first dominator edge; determining a second dominator edge and a second set of dominated gates in the circuit, the second set of dominated gates coupled to the first primary input lead and to a second set of edges of the plurality of edges dominated by the second dominator edge; determining a third set of dominated gates, the third set of dominated gates including gates dominated by only the first dominator edge; determining a fourth set of dominated gates, the fourth set of dominated gates including gates dominated by the first dominator edge and the second dominator edge; providing a first dominator selector circuit to the circuit; providing a second dominator selector circuit to the circuit; coupling the first dominator selector circuit to the first dominator edge and to the first primary input lead; coupling the second dominator selector circuit to the second dominator edge and to the first dominator selector circuit; uncoupling the first primary input lead from the first set of dominated gates; coupling the third set of dominated gates to the first dominator selector circuit; and coupling the fourth set of dominated gates to the second dominator selector circuit.
Claim 9
Independent Claim
270 words
A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the method comprising the steps of: determining a first dominator edge and a first set of dominated gates in the circuit, the first set of dominated gates coupled to the first primary input lead and to a first set edges of the plurality of edges dominated by the first dominator edge; determining a second dominator edge and a second set of dominated gates in the circuit, the second set of dominated gates coupled to the first primary input lead and to a second set of edges of the plurality of edges dominated by the second dominator edge; determining a third set of dominated gates, the third set of dominated gates including gates dominated by only the first dominator edge; determining a fourth set of dominated gates, the fourth set of dominated gates including gates dominated by the first dominator edge and the second dominator edge; providing a first dominator selector circuit to the circuit; providing a second dominator selector circuit to the circuit; coupling the first dominator selector circuit to the first dominator edge and to the first primary input lead; coupling the second dominator selector circuit to the second dominator edge and to the first dominator selector circuit; uncoupling the first primary input lead from the first set of dominated gates; coupling the third set of dominated gates to the first dominator selector circuit; and coupling the fourth set of dominated gates to the second dominator selector circuit.
Claim 10
Dependent Claim
333 words
The method of claim 7, wherein the first set of dominated gates each have a first input and a second input, the first inputs of the first set of dominated gates coupled to the first primary input lead, the second inputs of the first set of dominated gates coupled to edges of the plurality of edges dominated by the first dominator edge; wherein the second set of dominated gates each have a first input and a second input, the first inputs of the second set of dominated gates coupled to the first primary input lead, the second inputs of the second set of dominated gates coupled to edges of the plurality of edges dominated by the second dominator edge; wherein the first dominator selector circuit has at least a first and a second input and an output; wherein the second dominator selector circuit has at least a first and a second input and an output; wherein the step of coupling the first dominator selector circuit comprises steps of: coupling the first input of the first dominator selector circuit to the first dominator edge; and coupling the second input of the first dominator selector circuit to the first primary input lead; wherein the step of coupling the second dominator selector circuit comprises; the steps of: coupling the first input of the second dominator selector circuit to the second dominator edge; and coupling the second input of the second dominator selector circuit to the output of the first dominator selector circuit; wherein the step of uncoupling comprises uncoupling the first inputs of the first set of dominated gates from the first primary input lead; wherein the step of coupling the third set of gates comprises coupling first inputs of the third set of dominated gates to the output of the first dominator selector circuit; and wherein the step of coupling the fourth set of gates comprises coupling first inputs of the fourth set of dominated gates to the output of the second dominator selector circuit.
Claim 11
Dependent Claim
20 words
The method of claim 7 wherein, the first dominator selector circuit and the second dominator selector circuit are AND gates.
Claim 12
Dependent Claim
11 words
A circuit produced in accordance with the process of claim 7.
Claim 13
Dependent Claim
52 words
The method of claim 7, wherein the step of determining a second dominator edge and a second set of dominated gates comprises the steps of: determining a dominator set of edges and the second set of dominated gates; and ORing the dominator set of edges together to determine the second dominator edge.
Claim 14
Independent Claim
279 words
A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the method comprising the steps of: determining a first dominator edge and a first set of dominated gates in the circuit, the first set of dominated gates each having a first input and a second input, the first inputs of the first set of dominated gates coupled to the first primary input lead, the second inputs of the first set of dominated gates coupled to edges of the plurality of edges dominated by the first dominator edge; determining a second dominator edge and a second set of dominated gates in the circuit, the second set of dominated gates each having a first input and a second input, the first inputs of the second set of dominated gates coupled to the first primary input lead, the second inputs of the second set of dominated gates coupled to edges of the plurality of edges dominated by the second dominator edge, the second set of dominated gates being a subset of the first set of dominated gates; providing an AND gate to the circuit, the AND gate having at least a first and a second input and an output; coupling the first input of the AND gate to the first dominator edge; coupling the second input of the AND gate to the first primary input lead; uncoupling the first inputs of the first set of dominated gates from the first primary input lead; and coupling the first inputs of the first set of dominated gates to the output of AND gate.
Claim 15
Independent Claim
279 words
A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the method comprising the steps of: determining a first dominator edge and a first set of dominated gates in the circuit, the first set of dominated gates each having a first input and a second input, the first inputs of the first set of dominated gates coupled to the first primary input lead, the second inputs of the first set of dominated gates coupled to edges of the plurality of edges dominated by the first dominator edge; determining a second dominator edge and a second set of dominated gates in the circuit, the second set of dominated gates each having a first input and a second input, the first inputs of the second set of dominated gates coupled to the first primary input lead, the second inputs of the second set of dominated gates coupled to edges of the plurality of edges dominated by the second dominator edge, the second set of dominated gates being a subset of the first set of dominated gates; providing an AND gate to the circuit, the AND gate having at least a first and a second input and an output; coupling the first input of the AND gate to the first dominator edge; coupling the second input of the AND gate to the first primary input lead; uncoupling the first inputs of the first set of dominated gates from the first primary input lead; and coupling the first inputs of the first set of dominated gates to the output of AND gate.
Claim 16
Dependent Claim
11 words
A circuit produced in accordance with the process of claim 12.
Claim 17
Independent Claim
180 words
A system for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the system including a processor and a memory, the system further comprising: an input device, coupled to the memory for inputting a Shannon graph into the memory; means, coupled to the memory for determining a dominator edge and dominated gates in the circuit, the dominated gates coupled to the first primary input lead and to edges of the plurality of edges dominated by the dominator edge; means, coupled to the memory for providing a dominator selector circuit to the circuit; means, coupled to the memory for coupling the dominator selector circuit to the dominator edge and to the first primary input lead; means, coupled to the memory for uncoupling the dominated gates from the first primary input lead; means, coupled to the memory for coupling the dominated gates to the dominator selector circuit; and an output device, coupled to the processor and to the memory for outputting; the circuit.
Claim 18
Independent Claim
180 words
A system for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the system including a processor and a memory, the system further comprising: an input device, coupled to the memory for inputting a Shannon graph into the memory; means, coupled to the memory for determining a dominator edge and dominated gates in the circuit, the dominated gates coupled to the first primary input lead and to edges of the plurality of edges dominated by the dominator edge; means, coupled to the memory for providing a dominator selector circuit to the circuit; means, coupled to the memory for coupling the dominator selector circuit to the dominator edge and to the first primary input lead; means, coupled to the memory for uncoupling the dominated gates from the first primary input lead; means, coupled to the memory for coupling the dominated gates to the dominator selector circuit; and an output device, coupled to the processor and to the memory for outputting; the circuit.
Claim 19
Dependent Claim
164 words
The system of claim 14, wherein the dominated gates each have at least a first input and a second input, the first inputs of the dominated gates coupled to the first primary input lead, the second inputs of the dominated gates coupled to edges of the plurality of edges dominated by the dominator edge; wherein the dominator selector circuit has at least a first and a second input and an output; wherein the means for coupling the dominator selector circuit comprises: means for coupling the first input of the dominator selector circuit to the dominator edge; and means for coupling the second input of the dominator selector circuit to the first primary input lead; wherein the means for uncoupling comprises means for uncoupling the first inputs of the dominated gates from the first primary input lead; and wherein the means for coupling the dominated gates comprises means for coupling the first inputs of the dominated gates to the output of the dominator selector circuit.
Claim 20
Independent Claim
372 words
A system for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the system including a processor and a memory, the system further comprising: an input device, coupled to the memory for inputting a Shannon graph into the memory; means, coupled to the memory for determining a first dominator edge and a first set of dominated gates in the circuit, the first set of dominated gates coupled to the first primary input lead and to a first set of edges of the plurality of edges dominated by the first dominator edge; means, coupled to the memory for determining a second dominator edge and a second set of dominated gates in the circuit, the second set of dominated gates coupled to the first primary input lead and to a second set of edges of the plurality of edges dominated by the second dominator edge; means, coupled to the memory for determining a third set of dominated gates, the third set of dominated gates including gates dominated by only the first dominator edge; means, coupled to the memory for determining a fourth set of dominated gates, the fourth set of dominated gates including gates dominated by the first dominator edge and the second dominator edge; means, coupled to the memory for providing a first dominator selector circuit to the circuit; means, coupled to the memory for providing a second dominator selector circuit to the circuit; means, coupled to the memory for coupling the first dominator selector circuit to the first dominator edge and to the first primary input lead; means, coupled to the memory for coupling the second dominator selector circuit to the second dominator edge and to the first dominator selector circuit; means, coupled to the memory for uncoupling the primary input lead from the first set of dominated gates; means, coupled to the memory for coupling the third set of dominated gates to the first dominator selector circuit; means, coupled to the memory for coupling the fourth set of dominated gates to the second dominator selector circuit; and an output device, coupled to the processor and to the memory for outputting the circuit.
Claim 21
Independent Claim
372 words
A system for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the system including a processor and a memory, the system further comprising: an input device, coupled to the memory for inputting a Shannon graph into the memory; means, coupled to the memory for determining a first dominator edge and a first set of dominated gates in the circuit, the first set of dominated gates coupled to the first primary input lead and to a first set of edges of the plurality of edges dominated by the first dominator edge; means, coupled to the memory for determining a second dominator edge and a second set of dominated gates in the circuit, the second set of dominated gates coupled to the first primary input lead and to a second set of edges of the plurality of edges dominated by the second dominator edge; means, coupled to the memory for determining a third set of dominated gates, the third set of dominated gates including gates dominated by only the first dominator edge; means, coupled to the memory for determining a fourth set of dominated gates, the fourth set of dominated gates including gates dominated by the first dominator edge and the second dominator edge; means, coupled to the memory for providing a first dominator selector circuit to the circuit; means, coupled to the memory for providing a second dominator selector circuit to the circuit; means, coupled to the memory for coupling the first dominator selector circuit to the first dominator edge and to the first primary input lead; means, coupled to the memory for coupling the second dominator selector circuit to the second dominator edge and to the first dominator selector circuit; means, coupled to the memory for uncoupling the primary input lead from the first set of dominated gates; means, coupled to the memory for coupling the third set of dominated gates to the first dominator selector circuit; means, coupled to the memory for coupling the fourth set of dominated gates to the second dominator selector circuit; and an output device, coupled to the processor and to the memory for outputting the circuit.
Claim 22
Dependent Claim
380 words
The system of claim 16, wherein the first set of dominated gates each have a first input and a second input, the first inputs of the first set of dominated gates coupled to the first primary input lead, the second inputs of the first set of dominated gates coupled to edges Of the plurality of edges dominated by the first dominator edge; wherein the fourth set of dominated gates each have a first input and a second input, the first inputs of the fourth set of dominated gates coupled to the first primary input lead, the second inputs of the fourth set of dominated gates coupled to edges of the plurality of edges dominated by the first dominator edge and by the second dominator edge; wherein the first dominator selector circuit has at least a first and a second input and an output; wherein the second dominator selector circuit has at least a first and a second input and an output; wherein the means for coupling the first dominator selector circuit comprises: means for coupling the first input of the first dominator selector circuit to the first dominator edge; and means for coupling the second input of the first dominator selector circuit to the first primary input lead; wherein the means for coupling the second dominator selector circuit comprises: means for coupling the first input of the second dominator selector circuit to the second dominator edge; and means for coupling the second input of the second dominator selector circuit to the output of the first dominator selector circuit; wherein the means for uncoupling comprises means for uncoupling the first inputs of the first set of dominated gates from the first primary input lead; wherein the third set of gates is a subset of the first set of gates; wherein the fourth set of gates is a subset of the first set of gates; wherein the means for coupling the third set of gates comprises means for coupling the first inputs of the third set of dominated gates to the output of the first dominator selector circuit; and wherein the means for coupling the fourth set of gates comprises means for coupling the first inputs of the fourth set of dominated gates to the output of the second dominator selector circuit.
Claim 23
Dependent Claim
151 words
A computer system for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the computer system comprising: a computer readable storage medium comprising: code for accepting as input a Shannon graph; code for determining a dominator edge and dominated gates in the circuit, the dominated gates coupled to the first primary input lead and to edges of the plurality of edges dominated by the dominator edge; code for providing a dominator selector circuit to the circuit; code for coupling the dominator selector circuit to the dominator edge and to the first primary input lead; code for uncoupling the dominated gates from the first primary input lead; and code for coupling the dominated gates to the dominator selector circuit; and a processor coupled to the computer readable storage medium for executing said codes.
Claim 24
Dependent Claim
151 words
A computer system for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the computer system comprising: a computer readable storage medium comprising: code for accepting as input a Shannon graph; code for determining a dominator edge and dominated gates in the circuit, the dominated gates coupled to the first primary input lead and to edges of the plurality of edges dominated by the dominator edge; code for providing a dominator selector circuit to the circuit; code for coupling the dominator selector circuit to the dominator edge and to the first primary input lead; code for uncoupling the dominated gates from the first primary input lead; and code for coupling the dominated gates to the dominator selector circuit; and a processor coupled to the computer readable storage medium for executing said codes.
Claim 25
Dependent Claim
165 words
The computer system of claim 18, wherein the dominated gates each have at least a first input and a second input, the first inputs of the dominated gates coupled to the first primary input lead, the second inputs of the dominated gates coupled to edges of the plurality of edges dominated by the dominator edge; wherein the dominator selector circuit has at least a first and a second input and an output; wherein the code for coupling the dominator selector circuit comprises: code for coupling the first input of the dominator selector circuit to the dominator edge; and code for coupling the second input of the dominator selector circuit to the first primary input lead; wherein the code for uncoupling comprises code for uncoupling the first inputs of the dominated gates from the first primary input lead; and wherein the code for coupling the dominated gates comprises code for coupling the first inputs of the dominated gates to the output of the dominator selector circuit.
Claim 26
Dependent Claim
15 words
The computer system of claim 18 wherein, the dominator selector circuit is an AND gate.
Claim 27
Dependent Claim
314 words
A computer system for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the computer system comprising: code for accepting as input a Shannon graph; code for determining a first dominator edge and a first set of dominated gates in the circuit, the first set of dominated gates coupled to the first primary input lead and to a first set of edges of the plurality of edges dominated by the first dominator edge; code for determining a second dominator edge and a second set of dominated gates in the circuit, the second set of dominated gates coupled to the first primary input lead and to a second set of edges of the plurality of edges dominated by the second dominator edge; code for determining a third set of dominated gates, the fourth set of dominated gates including gates dominated by only the first dominator edge; code for determining a fourth set of dominated gates, the fourth set of dominated gates including gates dominated by the first dominator edge and the second dominator edge; code for providing a first dominator selector circuit to the circuit; code for providing a second dominator selector circuit to the circuit; code for coupling the first dominator selector circuit to the first dominator edge and to the first primary input lead; code for coupling the second dominator selector circuit to the second dominator edge and to the first dominator selector circuit; code for uncoupling the primary input lead from the first set of dominated gates; code for coupling the third set of dominated gates to the first dominator selector circuit; code for coupling the fourth set of dominated gates to the second dominator selector circuit; a computer readable storage medium for storing said codes; and a processor for executing said codes.
Claim 28
Dependent Claim
314 words
A computer system for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the computer system comprising: code for accepting as input a Shannon graph; code for determining a first dominator edge and a first set of dominated gates in the circuit, the first set of dominated gates coupled to the first primary input lead and to a first set of edges of the plurality of edges dominated by the first dominator edge; code for determining a second dominator edge and a second set of dominated gates in the circuit, the second set of dominated gates coupled to the first primary input lead and to a second set of edges of the plurality of edges dominated by the second dominator edge; code for determining a third set of dominated gates, the fourth set of dominated gates including gates dominated by only the first dominator edge; code for determining a fourth set of dominated gates, the fourth set of dominated gates including gates dominated by the first dominator edge and the second dominator edge; code for providing a first dominator selector circuit to the circuit; code for providing a second dominator selector circuit to the circuit; code for coupling the first dominator selector circuit to the first dominator edge and to the first primary input lead; code for coupling the second dominator selector circuit to the second dominator edge and to the first dominator selector circuit; code for uncoupling the primary input lead from the first set of dominated gates; code for coupling the third set of dominated gates to the first dominator selector circuit; code for coupling the fourth set of dominated gates to the second dominator selector circuit; a computer readable storage medium for storing said codes; and a processor for executing said codes.
Claim 29
Dependent Claim
381 words
The computer system of claim 21, wherein the first set of dominated gates each have a first input and a second input, the first inputs of the first set of dominated gates coupled to the first primary input lead, the second inputs of the first set of dominated gates coupled to edges of the plurality of edges dominated by the first dominator edge; wherein the fourth set of dominated gates each have a first input and a second input, the first inputs of the fourth set of dominated gates coupled to the first primary input lead, the second inputs of the fourth set of dominated gates coupled to edges of the plurality of edges dominated by the first dominator edge and by the second dominator edge; wherein the first dominator selector circuit has at least a first and a second input and an output; wherein the second dominator selector circuit has at least a first and a second input and an output; wherein the code for coupling the first dominator selector circuit comprises: code for coupling the first input of the first dominator selector circuit to the first dominator edge; and code for coupling the second input of the first dominator selector circuit to the first primary input lead; wherein the code for coupling the second dominator selector circuit comprises: code for coupling the first input of the second dominator selector circuit to the second dominator edge; and code for coupling the second input of the second dominator selector circuit to the output of the first dominator selector circuit; wherein the code for uncoupling comprises code for uncoupling the first inputs of the first set of dominated gates from the first primary input lead; wherein the third set of gates is a subset of the first set of gates; wherein the fourth set of gates is a subset of the first set of gates; wherein the code for coupling the third set of gates comprises code for coupling the first inputs of the third set of dominated gates to the output of the first dominator selector circuit; and wherein the code for coupling the fourth set of gates comprises code for coupling the first inputs of the fourth set of dominated gates to the output of the second dominator selector circuit.
Claim 30
Dependent Claim
139 words
A computer program product for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the computer program product comprising: a computer readable storage medium comprising: code for accepting as input a Shannon graph; code for determining a dominator edge and dominated gates in the circuit, the dominated gates coupled to the first primary input lead and to edges of the plurality of edges dominated by the dominator edge; code for providing a dominator selector circuit to the circuit; code for coupling the dominator selector circuit to the dominator edge and to the first primary input lead; code for uncoupling the dominated gates from the first primary input lead; and code for coupling the dominated gates to the dominator selector circuit.
Claim 31
Dependent Claim
139 words
A computer program product for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the computer program product comprising: a computer readable storage medium comprising: code for accepting as input a Shannon graph; code for determining a dominator edge and dominated gates in the circuit, the dominated gates coupled to the first primary input lead and to edges of the plurality of edges dominated by the dominator edge; code for providing a dominator selector circuit to the circuit; code for coupling the dominator selector circuit to the dominator edge and to the first primary input lead; code for uncoupling the dominated gates from the first primary input lead; and code for coupling the dominated gates to the dominator selector circuit.
Claim 32
Dependent Claim
166 words
The computer program product of claim 23, wherein the dominated gates each have at least a first input and a second input, the first inputs of the dominated gates coupled to the first primary input lead, the second inputs of the dominated gates coupled to edges of the plurality of edges dominated by the dominator edge; wherein the dominator selector circuit has at least a first and a second input and an output; wherein the code for coupling the dominator selector circuit comprises: code for coupling the first input of the dominator selector circuit to the dominator edge; and code for coupling the second input of the dominator selector circuit to the first primary input lead; wherein the code for uncoupling comprises code for uncoupling the first inputs of the dominated gates from the first primary input lead; and wherein the code for coupling the dominated gates comprises code for coupling the first inputs of the dominated gates to the output of the dominator selector circuit.
Claim 33
Dependent Claim
16 words
The computer program product of claim 23 wherein, the dominator selector circuit is an AND gate.
Claim 34
Dependent Claim
310 words
A computer program product for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the computer program product comprising: code for accepting as input a Shannon graph; code for determining a first dominator edge and a first set of dominated gates in the circuit, the first set of dominated gates coupled to the first primary input lead and to a first set of edges of the plurality of edges dominated by the first dominator edge; code for determining a second dominator edge and a second set of dominated gates in the circuit, the second set of dominated gates coupled to the first primary input lead and to a second set of edges of the plurality of edges dominated by the second dominator edge; code for determining a third set of dominated gates, the fourth set of dominated gates including gates dominated by only the first dominator edge; code for determining a fourth set of dominated gates, the fourth set of dominated gates including gates dominated by the first dominator edge and the second dominator edge; code for providing a first dominator selector circuit to the circuit; code for providing a second dominator selector circuit to the circuit; code for coupling the first dominator selector circuit to the first dominator edge and to the first primary input lead; code for coupling the second dominator selector circuit to the second dominator edge and to the first dominator selector circuit; code for uncoupling the primary input lend from the first set of dominated gates; code for coupling the third set of dominated gates to the first dominator selector circuit; code for coupling the fourth set of dominated gates to the second dominator selector circuit; and a computer readable storage medium for storing said codes.
Claim 35
Dependent Claim
310 words
A computer program product for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the computer program product comprising: code for accepting as input a Shannon graph; code for determining a first dominator edge and a first set of dominated gates in the circuit, the first set of dominated gates coupled to the first primary input lead and to a first set of edges of the plurality of edges dominated by the first dominator edge; code for determining a second dominator edge and a second set of dominated gates in the circuit, the second set of dominated gates coupled to the first primary input lead and to a second set of edges of the plurality of edges dominated by the second dominator edge; code for determining a third set of dominated gates, the fourth set of dominated gates including gates dominated by only the first dominator edge; code for determining a fourth set of dominated gates, the fourth set of dominated gates including gates dominated by the first dominator edge and the second dominator edge; code for providing a first dominator selector circuit to the circuit; code for providing a second dominator selector circuit to the circuit; code for coupling the first dominator selector circuit to the first dominator edge and to the first primary input lead; code for coupling the second dominator selector circuit to the second dominator edge and to the first dominator selector circuit; code for uncoupling the primary input lend from the first set of dominated gates; code for coupling the third set of dominated gates to the first dominator selector circuit; code for coupling the fourth set of dominated gates to the second dominator selector circuit; and a computer readable storage medium for storing said codes.
Claim 36
Dependent Claim
376 words
The computer program product of claim 26, wherein the first set of dominated gates each have a first input and a second input, the first inputs of the first set of dominated gates coupled to the first primary input lead, the second inputs of the first set of dominated gates coupled to edges of the plurality of edges dominated by the first dominator edge; wherein the fourth set of dominated gates each have a first input and a second input, the first inputs of the fourth set of dominated gates coupled to the first primary input lead, the second inputs of the fourth set of dominated gates coupled to edges of the plurality of edges dominated by the second dominator edge; wherein the first dominator selector circuit has at least a first and a second input and an output; wherein the second dominator selector circuit has at least a first and a second input and an output; wherein the code for coupling the first dominator selector circuit comprises: code for coupling the first input of the first dominator selector circuit to the first dominator edge; and code for coupling the second input of the first dominator selector circuit to the first primary input lead; wherein the code for coupling the second dominator selector circuit comprises: code for coupling the first input of the second dominator selector circuit to the second dominator edge; and code for coupling the second input of the second dominator selector circuit to the output of the first dominator selector circuit; wherein the code for uncoupling comprises code for uncoupling the first inputs of the first set of dominated gates from the first primary input lead; wherein the third set of gates is a subset of the first set of gates; wherein the fourth set of gates is a subset of the first set of gates; wherein the code for coupling the third set of gates comprises code for coupling the first inputs of the third set of dominated gates to the output of the first dominator selector circuit; and wherein the code for coupling the fourth set of gates comprises code for coupling the first inputs of the fourth set of dominated gates to the output of the second dominator selector circuit.
References Cited (Backward Citations)
US5461574A
Cited
US5243538A
Cited
US5243538B1
Cited
US5377201A
Cited
US5396435A
Cited
US5396425A
Cited
US5469367A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-14 | 2001-01-13 | 2001-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-14 | 2005-01-13 | 2005-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-14 | 2009-01-13 | 2009-07-15 | $7700.00 | Window Closed / Lapsed |