Nonvolatile semiconductor memory device

Claim 1

A multi-level non-volatile semiconductor memory device comprising: a semiconductor substrate; a plurality of bit lines; a plurality of word lines insulatively intersecting said bit lines; a memory cell array comprising a plurality of memory cells, each including a transistor with a charge storage portion and having written states of first, second, . . . , (n-1)th and nth (n not less than 3) storage levels; a plurality of first data storage circuits for storing first data of first and second signal levels which respectively define write voltages and non-write voltages being applied to respective of said memory cells, wherein said write voltages correspond to said first signal level and promote progress of writing of data into said respective of said memory cells and said non-write voltages correspond to said second signal level and restrain writing of data into said respective of said memory cells so as to keep the written states of said memory cells; a plurality of second data storage circuits, each coupled to each of said first data storage circuits, for storing second data of second, third, . . . , (n-1)th and nth logic levels; and a plurality of programming control circuits including said first and second data storage circuits for applying said write voltages to the memory cells corresponding to the first data storage circuits storing the first data of said first signal level, for determining actual written states of said memory cells, for modifying stored first data from said first signal level to said second signal level in the first data storage circuits storing the first data of said first signal level and corresponding to the second data storage circuits storing the second data of said ith (i=2,3, . . . ,n-1,n) logic level and the memory cells in which successful writing of said ith (respectively, i=2,3, . . . , n-1,n) storage level has been determined, for maintaining said stored first data at said first signal level in the first data storage circuits storing the first data of said first signal level and corresponding to the second data storage circuits storing the second data of said ith (i=2,3, . . . ,n-1,n) logic level and the memory cells in which it has been determined that said ith (respectively, i=2,3, . . . ,n-1,n) storage level has not been successfully written, and for maintaining said stored first data at said second signal level in the first data storage circuits storing the first data of said second signal level.