Data resynchronization

Claim 2

An array of digital data processing nodes arrayed in at least one node-ring and having an external transmission clock provided for each said node-ring, wherein each said node has its own internal transmission-clock set at approximately the same frequency as said external transmission-clock; and wherein data is transferred in data-packets; plus the combination, with said array of nodes, of data-resynchronizing means comprising a first-in-first-out (FIFO) array of prescribed like register means arranged in a circular first-in, first-out (FIFO) arrangement, and including a multiplex stage comprising a set of N registers operated in first-in, first-out fashion, where N is a positive integer.

Claim 3

The invention of claim 1, comprising six FIFO registers, arranged in two like sets, each comprising three registers.

Claim 4

The invention of claim 1, wherein the signals from said external and internal clocks are generated by different source means and are applied to a multiplex stage, these signals having the nominal frequency of their source means but being subject to "drifting" apart.

Claim 5

The invention of claim 1, wherein said circular FIFO arrangement includes a multiplex stage which, in turn, comprises an input-multiplex unit which presents input to said node ring and an output multiplex unit which presents output from said node ring.

Claim 6

The invention of claim 4, wherein said input-multiplex stage comprises N registers arrayed so that data is input thereto in sequential circular fashion, where N is a positive integer.

Claim 7

The invention of claim 5, wherein said N registers are arrayed so that, in said ring, the read-point is opposed to the write point at the beginning of a data packet, which is then quickly read-out before significant inter-clock-drift can occur.

Claim 8

The invention of claim 6, wherein the said multiplex stage is arranged to include means for resynchronizing of read-point with write-point to correct clock-drift between packets and without compromising data.

Claim 9

For a set of digital data processing nodes arrayed in at least one node-ring where each node has its own local transmission-clock which is approximately the same frequency as the transmission-clock of other nodes in the ring, where said node-ring is made to comprise a circular array of N registers operated in first-in/first-out (FIFO) fashion, where N is a positive integer, said N registers being made to include six FIFO registers, arrayed in two sets of three registers and where data is transferred in data-packets, the method of resynchronizing data transfer comprising: developing a FIFO array of prescribed like register means disposed as a circular first-in, first-out array wherein said FIFO array also includes an input-multiplex portion and an output multiplex portion; and wherein said input-multiplex portion is made to comprise N registers arrayed so that data is input thereto in sequential circular fashion; where N is a positive integer; and applying said FIFO array in said node-ring.

Claim 10

For a set of digital data processing nodes arrayed in at least one node-ring where each node has its own local transmission-clock which is approximately the same frequency as the transmission-clock of other nodes in the ring, where said node-ring is made to comprise a circular array of N registers operated in first-in/first-out (FIFO) fashion, where N is a positive integer, said N registers being made to include six FIFO registers, arrayed in two sets of three registers and where data is transferred in data-packets, the method of resynchronizing data transfer comprising: developing a FIFO array of prescribed like register means disposed as a circular first-in, first-out array wherein said FIFO array also includes an input-multiplex portion and an output multiplex portion; and wherein said input-multiplex portion is made to comprise N registers arrayed so that data is input thereto in sequential circular fashion; where N is a positive integer; and applying said FIFO array in said node-ring.

Claim 11

The method of claim 8, wherein said N registers are arrayed in a circle with the read-point is opposed to the write point at the beginning of a data packet, which is then quickly read-out before significant inter-clock-drift can occur; and wherein inter-clock drift is compensated for between packets.

Claim 12

The method of claim 9, wherein the said multiplex stage is arranged to include means for resynchronizing of read-point with write-point to correct clock-drift between packets, and without compromising data.