Nonvolatile semiconductor memory device in which band to band tunneling current is suppressed

Claim 2

A nonvolatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a first impurity region of a second conductivity type formed on a surface of the semiconductor substrate; a second impurity region of the first conductivity type formed in the first impurity region of the second conductivity type; a gate oxide film formed on a surface of the second impurity region of the first conductivity type; a floating gate formed on the gate oxide film; an insulting film formed on the floating gate; a control gate formed on the insulating film; source and drain regions of the second conductivity type formed in the second impurity region of the first conductivity type; and voltage supplying means for discharging the floating gate, the voltage supplying means being controlled such that the semiconductor substrate is grounded and a potential difference between one of the source and drain regions and the second impurity region of the first conductivity type is greater than 0 V and smaller than 2.5 V.

Claim 3

A nonvolatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a first impurity region of a second conductivity type formed on a surface of the semiconductor substrate; a second impurity region of the first conductivity type formed in the first impurity region of the second conductivity type; a gate oxide film formed on a surface of the second impurity region of the first conductivity type; a floating gate formed on the gate oxide film; an insulting film formed on the floating gate; a control gate formed on the insulating film; source and drain regions of the second conductivity type formed in the second impurity region of the first conductivity type; and voltage supplying means for discharging the floating gate, the voltage supplying means being controlled such that the semiconductor substrate is grounded, a potential difference between one of the source and drain regions and the second impurity region of the first conductivity type is greater than 0 V and smaller than 2.5 V, and voltages a, b, c and d respectively supplied to the control gate, the second impurity region, the semiconductor substrate, and one of the source and drain regions have a relationship of d>b>c>a.

Claim 4

A nonvolatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a first impurity region of a second conductivity type formed on a surface of the semiconductor substrate; a second impurity region of the first conductivity type formed in the first impurity region of the second conductivity type; a gate oxide film formed on a surface of the second impurity region of the first conductivity type; a floating gate formed on the gate oxide film; an insulting film formed on the floating gate; a control gate formed on the insulating film; source and drain regions of the second conductivity type formed in the second impurity region of the first conductivity type; and voltage supplying means for discharging the floating gate, the voltage supplying means being controlled such that the semiconductor substrate is grounded, a potential difference between one of the source and drain regions and the second impurity region of the first conductivity type is greater than 0 V and smaller than 2.5 V, and voltages a, b, c and d respectively supplied to the control gate, the second impurity region, the semiconductor substrate, and one of the source and drain regions have a relationship of d>b>c>a.

Claim 5

The nonvolatile semiconductor memory device according to claim 1 or 2, wherein the voltage supplying means include a structure for supplying a voltage of the same potential as that in the second impurity region of the first conductivity type to the first impurity region of the second conductivity type, when the floating gate is discharged.

Claim 6

The nonvolatile semiconductor memory device according to claim 1 or 2, wherein the voltage supplying means comprise: a booster circuit for boosting a source voltage; a level shift circuit connected to the booster circuit; and a switch circuit for supplying, in accordance with an output of the level shift circuit, a voltage corresponding to the source voltage to the second impurity region through an impurity region of the first conductivity type of a concentration higher than that of the second impurity region.

Claim 7

The nonvolatile semiconductor memory device according to claim 4, wherein the voltage corresponding to the source voltage is supplied, by means of the switch circuit, not only to the second impurity region but also to the first impurity region through an impurity region of the second conductivity type of a concentration higher than that of the first impurity region.

Claim 8

The nonvolatile semiconductor memory device according to claim 1 or 2, wherein the voltage supplying means comprise: a booster circuit for boosting a source voltage; a voltage regulation circuit for lowering the source voltage; a level shift circuit connected to the booster circuit; and a switch circuit for supplying, in accordance with an output of the level shift circuit, a voltage lowered from the source voltage by the voltage regulation circuit, to the second impurity region through an impurity region of the first conductivity type of a concentration higher than that of the second impurity region.

Claim 9

The nonvolatile semiconductor memory device according to claim 6, wherein the voltage lowered from the source voltage by the voltage regulation circuit is supplied, by means of the switch circuit, not only to the second impurity region but also to the first impurity region through an impurity region of the second conductivity type of a concentration higher than that of the first impurity region.

Claim 10

The nonvolatile semiconductor memory device according to claim 1 or 2, further comprising means for grounding the semiconductor substrate in all operation modes of the nonvolatile semiconductor memory device.

Claim 11

The nonvolatile semiconductor memory device according to claim 1 or 2, wherein charges are injected into the floating gate by hot electron injection.

Claim 12

The nonvolatile semiconductor memory device according to claim 1 or 2, wherein the voltage supplying means comprise: a booster circuit for boosting a source voltage; a level shift circuit connected to the booster circuit; a switch circuit for supplying, in accordance with an output of the level shift circuit, a voltage corresponding to the source voltage to the second impurity region through an impurity region of the first conductivity type of a concentration higher than that of the second impurity region; a word line driving circuit, connected to the booster circuit, for supplying to the control gate, a positive high potential for programming in a program operation and a negative high potential for erasing in an erase operation, in accordance with address data and an erase signal; and a source line driving circuit, connected to the booster circuit, for supplying to one of the source and drain regions, a potential of 0 V in said program operation and a potential lowered by an internal voltage regulation circuit, in accordance with address data.

Claim 13

The nonvolatile semiconductor memory device according to claim 1 or 2, wherein the voltage supplying means comprise: a booster circuit for boosting a source voltage; a voltage regulation circuit for lowering the source voltage; a level shift circuit connected to the booster circuit; a switch circuit for supplying, in accordance with an output of the level shift circuit, a voltage lowered from the source voltage by the voltage regulation circuit, to the second impurity region through an impurity region of the first conductivity type of a concentration higher than that of the second impurity region; a word line driving circuit, connected to the booster circuit, for supplying to the control gate, a positive high potential for programming in a program operation and a negative high potential for erasing in an erase operation, in accordance with address data and an erase signal; and a source line driving circuit, connected to the booster circuit, for supplying to one of the source and drain regions, a potential of 0 V in said program operation and a potential lowered by an internal voltage regulation circuit in said erase operation, in accordance with address data.

Claim 14

The nonvolatile semiconductor memory device according to claim 1 or 2, wherein the voltage supply means generate a Fowler-Nordheim tunneling current which flows through the gate oxide film, and extract electrons from the floating gate into one of the source and drain regions.