US5659519A
Expired / Lapsed
US
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Boosting voltage generator of semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-01-16
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Granted: 1997-08-19
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Expires: 2016-01-16
Abstract
Abstract A semiconductor memory device including at least two boosting voltage circuits which independently boost a supply voltage power level to a boosted voltage power level. A plurality of memory cell arrays each input the supply voltage power and store information therein. Driving circuits are connected to each of the memory cell arrays and supply the boosted voltage power to the memory cell arrays, the number of driving circuits preferably corresponding to the number of the boosting voltage circuits.
Inventors
- 👤 Hyun-Seok Lee
- 👤 Soo-In Cho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:34
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4085; G11C11/4074; G11C5/00; G11C5/14; G11C5/145
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
138 words
A portion of a single chip semiconductor memory device comprising: at least first and second boosting voltage circuits, which each independently boost a first voltage having a first voltage level to a second voltage having a second voltage level that is greater than said first voltage level; a plurality of memory cell arrays that input said second voltage as operational power and for storing information; and a plurality of driving circuits, each driving circuit connected to a different one of said memory cell arrays for supplying said second voltage to said memory cell arrays, said plurality of driving circuits divided into first and second driving circuit groups, said first driving circuit group inputting said second voltage from said first boosting voltage circuit and said second driving circuit group inputting said second voltage from said second boosting voltage circuit.
Claim 2
Dependent Claim
138 words
A portion of a single chip semiconductor memory device comprising: at least first and second boosting voltage circuits, which each independently boost a first voltage having a first voltage level to a second voltage having a second voltage level that is greater than said first voltage level; a plurality of memory cell arrays that input said second voltage as operational power and for storing information; and a plurality of driving circuits, each driving circuit connected to a different one of said memory cell arrays for supplying said second voltage to said memory cell arrays, said plurality of driving circuits divided into first and second driving circuit groups, said first driving circuit group inputting said second voltage from said first boosting voltage circuit and said second driving circuit group inputting said second voltage from said second boosting voltage circuit.
Claim 3
Dependent Claim
32 words
The semiconductor memory device as defined in claim 1, wherein each of said driving circuits is a word line driving circuit which supplies a boosted word line voltage to said memory array.
Claim 4
Dependent Claim
28 words
The semiconductor memory device as defined in claim 2, wherein said first voltage is a power supply voltage and said second voltage is said boosted word line voltage.
Claim 5
Dependent Claim
48 words
The semiconductor memory device as defined in claim 1, wherein said first voltage levels of respective ones of said first and second boosting voltage circuits are equal to each other and said second voltage levels of respective ones of said boosting voltage circuits are equal to each other.
Claim 6
Dependent Claim
179 words
A portion of a single chip semiconductor memory device comprising: a plurality of memory cell arrays, each memory cell array inputting a first voltage as operational power and containing a plurality of memory cells for storing information and a plurality of word lines for selecting said memory cells; a plurality of boosting voltage circuits which each independently boost a first voltage having a first voltage level to a second voltage having a second voltage level that is greater than said first voltage level, said plurality corresponding to a maximum number of said word lines that are activated in one period; and a plurality of driving circuits, each driving circuit connected to a different one of said memory cell arrays for supplying said second voltage to said memory cell arrays, said plurality of driving circuits divided into a plurality of driving circuit groups, said plurality corresponding in number to said number of said plurality of boosting voltage circuits, each of said plurality of driving circuit groups inputting said second voltage from a different one of said plurality of driving circuits.
Claim 7
Dependent Claim
179 words
A portion of a single chip semiconductor memory device comprising: a plurality of memory cell arrays, each memory cell array inputting a first voltage as operational power and containing a plurality of memory cells for storing information and a plurality of word lines for selecting said memory cells; a plurality of boosting voltage circuits which each independently boost a first voltage having a first voltage level to a second voltage having a second voltage level that is greater than said first voltage level, said plurality corresponding to a maximum number of said word lines that are activated in one period; and a plurality of driving circuits, each driving circuit connected to a different one of said memory cell arrays for supplying said second voltage to said memory cell arrays, said plurality of driving circuits divided into a plurality of driving circuit groups, said plurality corresponding in number to said number of said plurality of boosting voltage circuits, each of said plurality of driving circuit groups inputting said second voltage from a different one of said plurality of driving circuits.
Claim 8
Dependent Claim
28 words
The semiconductor memory device as defined in claim 5, wherein said first voltage is a power supply voltage, and said second voltage is a boosted word line voltage.
Claim 9
Dependent Claim
19 words
The semiconductor memory device as defined in claim 5, wherein said number of said boosting voltage circuits is eight.
Claim 10
Dependent Claim
28 words
The semiconductor memory device as defined in claim 7, wherein said first voltage is a power supply voltage, and said second voltage is a boosted word line voltage.
Claim 11
Dependent Claim
45 words
The semiconductor memory device as defined in claim 5, wherein said first voltage levels of respective ones of said boosting voltage circuits are equal to each other and said second voltage levels of respective ones of said boosting voltage circuits are equal to each other.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-08-18 | 2001-02-17 | 2001-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-18 | 2005-02-17 | 2005-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-18 | 2009-02-17 | 2009-08-19 | $7700.00 | Window Closed / Lapsed |