Semiconductor integrated circuit having logi gates

Claim 2

A semiconductor memory comprising: a plurality of memory cells; selecting means for selecting predetermined ones of said memory cells for reading and writing operations; data lines respectively coupled to said memory cells; a common write line coupled to said data lines through write transfer gates; a common read line coupled to said data lines through read transfer gates; and a control circuit for generating a writing control signal, wherein said read transfer gates disconnect said common read line from said data lines in response to a selection signal outputted by said selecting means and said writing control signal, when writing data in a selected memory cell.

Claim 3

A semiconductor memory according to claim 1, wherein said write transfer gates are comprised of MOS transistors having a channel of a first conductivity type, and wherein said read transfer gates are comprised of MOS transistors having a channel of a second conductivity type, opposite to said first conductivity type.

Claim 4

A semiconductor memory comprising: a plurality of memory cells; means for selecting a predetermined one of said memory cells; a write line for writing data into a selected memory cell; a read line for reading data from a selected memory cell; data lines which are connected to said memory cells and which are selectively connected to said read line through respective ones of first switches for electrically connecting a selected memory cell to said read line at a time of reading data from the selected memory cell and for electrically connecting said selected memory cell to said write line through respective ones of second switches at a time of writing data; and means for operating said first switches to disconnect said data lines from said read line at the time of writing data, said means including a control circuit for generating a writing control signal, wherein said first switches disconnect said common read line from said data lines in response to a selection signal outputted by said selecting means and said writing control signal, when writing data in a selected memory cell.

Claim 5

A semiconductor memory comprising: a plurality of memory cells; means for selecting a predetermined one of said memory cells; a write line for writing data into a selected memory cell; a read line for reading data from a selected memory cell; data lines which are connected to said memory cells and which are selectively connected to said read line through respective ones of first switches for electrically connecting a selected memory cell to said read line at a time of reading data from the selected memory cell and for electrically connecting said selected memory cell to said write line through respective ones of second switches at a time of writing data; and means for operating said first switches to disconnect said data lines from said read line at the time of writing data, said means including a control circuit for generating a writing control signal, wherein said first switches disconnect said common read line from said data lines in response to a selection signal outputted by said selecting means and said writing control signal, when writing data in a selected memory cell.

Claim 6

A semiconductor memory comprising: a plurality of memory cells; address circuitry for selecting a predetermined one of said memory cells; a write line for writing data into a selected memory cell; a read line for reading data from a selected memory cell; data lines which are connected to said memory cells and which are selectively electrically connected to said read line through respective ones of first transfer switches at a time of reading data from a memory cell and selectively electrically connected to said write line through respective ones of second transfer switches at the time of writing data into a memory cell; and a control circuit for generating a writing control signal, wherein said first switches disconnect said common read line from said data lines in response to a selection signal outputted by said address circuitry and said writing control signal, when writing data in a selected memory cell.

Claim 7

A semiconductor memory comprising: a plurality of memory cells; address circuitry for selecting a predetermined one of said memory cells; a write line for writing data into a selected memory cell; a read line for reading data from a selected memory cell; data lines which are connected to said memory cells and which are selectively electrically connected to said read line through respective ones of first transfer switches at a time of reading data from a memory cell and selectively electrically connected to said write line through respective ones of second transfer switches at the time of writing data into a memory cell; and a control circuit for generating a writing control signal, wherein said first switches disconnect said common read line from said data lines in response to a selection signal outputted by said address circuitry and said writing control signal, when writing data in a selected memory cell.

Claim 8

A semiconductor memory comprising: a memory cell array including memory cells arranged in a matrix and coupled to word lines and data lines; an address decoder for selecting a predetermined one of said memory cells; a common write line for writing data into each of said selected memory cells; a common read line for reading data from each of said selected memory cells; first means for connecting the data lines of the memory cell, selected at the time of reading data from a memory cell, to said common read line and for breaking the connection between said data lines of the memory cell, selected at the time of writing data into a memory cell, and said common read line; and second means for connecting said data lines of said memory cell, selected at the time of writing data into a memory cell, to said common write line; and a control circuit for generating a writing control signal, wherein said first means disconnects said common read line from said data lines in response to a selection signal outputted by said address decoder and said writing control signal, when writing data in a selected memory cell.

Claim 9

A semiconductor memory comprising: a memory cell array including memory cells arranged in a matrix and coupled to word lines and data lines; an address decoder for selecting a predetermined one of said memory cells; a common write line for writing data into each of said selected memory cells; a common read line for reading data from each of said selected memory cells; first means for connecting the data lines of the memory cell, selected at the time of reading data from a memory cell, to said common read line and for breaking the connection between said data lines of the memory cell, selected at the time of writing data into a memory cell, and said common read line; and second means for connecting said data lines of said memory cell, selected at the time of writing data into a memory cell, to said common write line; and a control circuit for generating a writing control signal, wherein said first means disconnects said common read line from said data lines in response to a selection signal outputted by said address decoder and said writing control signal, when writing data in a selected memory cell.

Claim 10

A semiconductor memory according to claim 2, wherein said plurality of memory cells are arranged in rows and columns, each row of memory cells being associated with a respective word line and each column of memory cells being associated with at least one data line.

Claim 11

A semiconductor memory according to claim 6, wherein a data line is selectively electrically connected to said common write line via a source-to-drain path of a MOS transistor of a corresponding transfer gate, during a write mode, in response to a column selection signal, wherein individual rows of memory cells are selected in response to word line selection signals corresponding thereto, and wherein said selecting means includes address decoding circuitry for outputting row and column selection signals.

Claim 12

A semiconductor memory according to claim 7, wherein said address decoding circuitry includes row and column decoders coupled to receive input signals corresponding to an X address and a Y address, respectively.

Claim 13

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns and coupled to word lines and data lines, each row of memory cells being associated with a respective word line and each column of memory cells being associated with at least one data line; selecting means for selecting predetermined ones of said memory cells for reading and writing operations, said selecting means including row and column decoders which are coupled to receive input signals corresponding to an X address and a Y address and which output row and column selection signals, respectively; a common write line coupled to said data lines through write transfer gates; a common read line coupled to said data lines through read transfer gates; control means coupled to said write transfer gates and to said read transfer gates for electrically connecting predetermined ones of said data lines, coupled to a selected memory cell, to said common write line during a write operation and for disconnecting said common read line from said predetermined data lines during said write operation; wherein said write transfer gates are comprised of MOS transistors having a channel of a first conductivity type, said read transfer gates are comprised of MOS transistors having a channel of a second conductivity type, opposite to said first conductivity type, each electrical connection of a data line to said common write lines is effected selectively through a source-to-drain path of a MOS transistor of a corresponding transfer gate, during a write mode, in response to a column selection signal, and individual rows of memory cells are selected in response to word line selection signals corresponding thereto; and wherein at least one of said row and column decoders is comprised of: a plurality of logic gates each including a first input terminal for receiving one of first input signals, an output terminal and a common connection terminal; a first switching element which comprises a transistor having a control electrode and first and second electrodes; a second switching element which comprises another transistor having a control electrode and first and second electrodes; a second input terminal, for receiving a second input signal, commonly connected to the control electrodes of the transistors of said first and second switching elements; and a second output terminal provided at a common connection of the second electrodes of the transistors of said first and second switching elements, wherein said first input signals and said second input signal are indicative of an input address, wherein said second output terminal is coupled to said common connection terminal of all of said plurality of logic gates, to thereby form a common node, and wherein said first and second switching elements operate complementary to one another in response to said second input signal.

Claim 14

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns and coupled to word lines and data lines, each row of memory cells being associated with a respective word line and each column of memory cells being associated with at least one data line; selecting means for selecting predetermined ones of said memory cells for reading and writing operations, said selecting means including row and column decoders which are coupled to receive input signals corresponding to an X address and a Y address and which output row and column selection signals, respectively; a common write line coupled to said data lines through write transfer gates; a common read line coupled to said data lines through read transfer gates; control means coupled to said write transfer gates and to said read transfer gates for electrically connecting predetermined ones of said data lines, coupled to a selected memory cell, to said common write line during a write operation and for disconnecting said common read line from said predetermined data lines during said write operation; wherein said write transfer gates are comprised of MOS transistors having a channel of a first conductivity type, said read transfer gates are comprised of MOS transistors having a channel of a second conductivity type, opposite to said first conductivity type, each electrical connection of a data line to said common write lines is effected selectively through a source-to-drain path of a MOS transistor of a corresponding transfer gate, during a write mode, in response to a column selection signal, and individual rows of memory cells are selected in response to word line selection signals corresponding thereto; and wherein at least one of said row and column decoders is comprised of: a plurality of logic gates each including a first input terminal for receiving one of first input signals, an output terminal and a common connection terminal; a first switching element which comprises a transistor having a control electrode and first and second electrodes; a second switching element which comprises another transistor having a control electrode and first and second electrodes; a second input terminal, for receiving a second input signal, commonly connected to the control electrodes of the transistors of said first and second switching elements; and a second output terminal provided at a common connection of the second electrodes of the transistors of said first and second switching elements, wherein said first input signals and said second input signal are indicative of an input address, wherein said second output terminal is coupled to said common connection terminal of all of said plurality of logic gates, to thereby form a common node, and wherein said first and second switching elements operate complementary to one another in response to said second input signal.

Claim 15

A semiconductor memory according to claim 9, wherein the transistor of said first switching element is an NMOS transistor having a gate, source and drain, the transistor of said second switching element is a PMOS transistor having a gate, source and drain, the gates of said NMOS transistor and said PMOS transistor are coupled to said second input terminal, and the drains of said NMOS and said PMOS transistors are coupled to said common node.

Claim 16

A semiconductor memory according to claim 10, wherein said NMOS and PMOS transistors are coupled as a CMOS inverter in which said PMOS transistor has its source coupled to receive an operating voltage of said memory, said NMOS transistor has its source coupled to receive either a predetermined reference potential or a logic signal output by a further CMOS inverter which has an input fed with a control signal, and said PMOS and NMOS transistors have drains commonly connected to said common node and gates commonly connected to said second input terminal.

Claim 17

A semiconductor memory according to claim 9, wherein each of said logic gates includes a first MOS transistor having a gate coupled to a corresponding said first input terminal and a source-drain path coupled between said output terminal thereof and said common node.

Claim 18

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns and coupled to word lines and data lines, each row of memory cells being associated with a respective word line and each column of memory cells being associated with at least one data line; selecting means for selecting predetermined ones of said memory cells for reading and writing operations, said selecting means including row and column decoders which are coupled to receive input signals corresponding to an X address and a Y address and which output row and column selection signals, respectively; a common write line coupled to said data lines through write transfer gates; a common read line coupled to said data lines through read transfer gates; control means coupled to said write transfer gates and to said read transfer gates for electrically connecting predetermined ones of said data lines, coupled a selected memory cell, to said common write line during a write operation and for disconnecting said common read line from said predetermined data lines during said write operation; wherein said write transfer gates are comprised of MOS transistors having a channel of a first conductivity type, said read transfer gates are comprised of MOS transistors having a channel of a second conductivity type, opposite to said first conductivity type, each electrical connection of a data line to said common write lines is effected selectively through a source-to-drain path of a MOS transistor of a corresponding transfer gate, during a write mode, in response to a column selection signal, and individual rows of memory cells are selected in response to word line selection signals corresponding thereto; and wherein at least one of said row and column decoders is comprised of: a plurality of logic gates coupled to a common node, respectively, each logic gate including a first input terminal for receiving ones of first input signals; a first switching element coupled to said common node; and a second switching element coupled to said common node, wherein said first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to said plurality of logic gates, said first and second switching elements operating complementary to one another in response to said second input signal, wherein said first input signals and said second input signal are indicative of an input address, and wherein each of said logic gates is comprised of a first MOS transistor having a gate coupled to said first input terminal thereof and a source-drain path coupled to said common node, and a second MOS transistor having a channel region of opposite conductivity type to the conductivity type of a channel region of said first MOS transistor, said second MOS transistor having a gate supplied with a predetermined reference potential and a source-drain path coupled in series with the source-drain path of said first MOS transistor between a power source potential terminal and said common node.

Claim 19

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns and coupled to word lines and data lines, each row of memory cells being associated with a respective word line and each column of memory cells being associated with at least one data line; selecting means for selecting predetermined ones of said memory cells for reading and writing operations, said selecting means including row and column decoders which are coupled to receive input signals corresponding to an X address and a Y address and which output row and column selection signals, respectively; a common write line coupled to said data lines through write transfer gates; a common read line coupled to said data lines through read transfer gates; control means coupled to said write transfer gates and to said read transfer gates for electrically connecting predetermined ones of said data lines, coupled a selected memory cell, to said common write line during a write operation and for disconnecting said common read line from said predetermined data lines during said write operation; wherein said write transfer gates are comprised of MOS transistors having a channel of a first conductivity type, said read transfer gates are comprised of MOS transistors having a channel of a second conductivity type, opposite to said first conductivity type, each electrical connection of a data line to said common write lines is effected selectively through a source-to-drain path of a MOS transistor of a corresponding transfer gate, during a write mode, in response to a column selection signal, and individual rows of memory cells are selected in response to word line selection signals corresponding thereto; and wherein at least one of said row and column decoders is comprised of: a plurality of logic gates coupled to a common node, respectively, each logic gate including a first input terminal for receiving ones of first input signals; a first switching element coupled to said common node; and a second switching element coupled to said common node, wherein said first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to said plurality of logic gates, said first and second switching elements operating complementary to one another in response to said second input signal, wherein said first input signals and said second input signal are indicative of an input address, and wherein each of said logic gates is comprised of a first MOS transistor having a gate coupled to said first input terminal thereof and a source-drain path coupled to said common node, and a second MOS transistor having a channel region of opposite conductivity type to the conductivity type of a channel region of said first MOS transistor, said second MOS transistor having a gate supplied with a predetermined reference potential and a source-drain path coupled in series with the source-drain path of said first MOS transistor between a power source potential terminal and said common node.

Claim 20

A semiconductor memory according to claim 13, wherein said predetermined reference potential is set at a value to keep said second MOS transistor in a constant ON state.

Claim 21

A semiconductor memory according to claim 13, wherein said first MOS transistor is a NMOS transistor, and wherein said second MOS transistor is a PMOS transistor.

Claim 22

A semiconductor memory according to claim 15, wherein said first switching element comprises a second NMOS transistor and said second switching element comprises a second PMOS transistor, said second NMOS transistor and said second PMOS transistor having gates thereof which are respectively coupled to said second input terminal and source-drain paths thereof which are respectively coupled to said common node.

Claim 23

A semiconductor memory according to claim 16, wherein said predetermined reference potential is set at ground to keep said second MOS transistor in a constant ON state.

Claim 24

A semiconductor memory according to claim 17, wherein an output terminal for each of said logic gates is provided between said source-drain paths of said first and second MOS transistors.

Claim 25

A semiconductor memory according to claim 18, further comprising a third switching element and a fourth switching element, wherein said third switching element includes a third NMOS transistor and said fourth switching element includes a third PMOS transistor, said third NMOS and PMOS transistors having gates coupled to a third input terminal for receiving a third input signal, and having source-drain paths commonly coupled, on the drain sides thereof, to a second common node which acts as an output providing the logic invert of said third input signal, wherein said plurality of logic gates includes first and second groups of logic gates, and wherein each NMOS transistor of the logic gates of said first group has its source thereof connected to said common node and to the drains of said second NMOS and PMOS transistors, the source of said second NMOS transistor being connected to said second common node which also commonly couples the output of said third NMOS and PMOS transistors to said second group of logic gates.

Claim 26

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns and coupled to word lines and data lines, each row of memory cells being associated with a respective word line and each column of memory cells being associated with at least one data line; selecting means for selecting predetermined ones of said memory cells for reading and writing operations, said selecting means including row and column decoders which are coupled to receive input signals corresponding to an X address and a Y address and which output row and column selection signals, respectively; a common write line coupled to said data lines through write transfer gates; a common read line coupled to said data lines through read transfer gates; control means coupled to said write transfer gates and to said read transfer gates for electrically connecting predetermined ones of said data lines, coupled to a selected memory cell, to said common write line during a write operation and for disconnecting said common read line from said predetermined data lines during said write operation; wherein said write transfer gates are comprised of MOS transistors having a channel of a first conductivity type, said read transfer gates are comprised of MOS transistors having a channel of a second conductivity type, opposite to said first conductivity type, each electrical connection of a data line to said common write lines is effected selectively through a source-to-drain path of a MOS transistor of a corresponding transfer gate, during a write mode, in response to a column selection signal, and individual rows of memory cells are selected in response to word line selection signals corresponding thereto; and wherein at least one of said row and column decoders is comprised of: a plurality of logic gates each including a first input terminal for receiving ones of first input signals, wherein said logic gates are coupled to a common node, respectively; a first switching element coupled to said common node; a second switching element coupled to said common node, wherein said first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to said plurality of logic gates, and wherein said first and second switching elements operate complementary to one another in response to said second input signal; and a switching circuit coupled to said common node, wherein said switching circuit is coupled to a third input terminal for receiving a third input signal, said third input signal together with said first input signals and said second input signal are indicative of an input address.

Claim 27

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns and coupled to word lines and data lines, each row of memory cells being associated with a respective word line and each column of memory cells being associated with at least one data line; selecting means for selecting predetermined ones of said memory cells for reading and writing operations, said selecting means including row and column decoders which are coupled to receive input signals corresponding to an X address and a Y address and which output row and column selection signals, respectively; a common write line coupled to said data lines through write transfer gates; a common read line coupled to said data lines through read transfer gates; control means coupled to said write transfer gates and to said read transfer gates for electrically connecting predetermined ones of said data lines, coupled to a selected memory cell, to said common write line during a write operation and for disconnecting said common read line from said predetermined data lines during said write operation; wherein said write transfer gates are comprised of MOS transistors having a channel of a first conductivity type, said read transfer gates are comprised of MOS transistors having a channel of a second conductivity type, opposite to said first conductivity type, each electrical connection of a data line to said common write lines is effected selectively through a source-to-drain path of a MOS transistor of a corresponding transfer gate, during a write mode, in response to a column selection signal, and individual rows of memory cells are selected in response to word line selection signals corresponding thereto; and wherein at least one of said row and column decoders is comprised of: a plurality of logic gates each including a first input terminal for receiving ones of first input signals, wherein said logic gates are coupled to a common node, respectively; a first switching element coupled to said common node; a second switching element coupled to said common node, wherein said first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to said plurality of logic gates, and wherein said first and second switching elements operate complementary to one another in response to said second input signal; and a switching circuit coupled to said common node, wherein said switching circuit is coupled to a third input terminal for receiving a third input signal, said third input signal together with said first input signals and said second input signal are indicative of an input address.

Claim 28

A semiconductor memory according to claim 20, wherein said switching circuit is comprised of at least one field effect transistor and at least one bipolar transistor.

Claim 29

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns and coupled to word lines and data lines, each row of memory cells being associated with a respective word line and each column of memory cells being associated with at least one data line; selecting means for selecting predetermined ones of said memory cells for reading and writing operations, said selecting means including row and column decoders which are coupled to receive input signals corresponding to an X address and a Y address and which output row and column selection signals, respectively; a common write line coupled to said data lines through write transfer gates; a common read line coupled to said data lines through read transfer gates; control means coupled to said write transfer gates and to said read transfer gates for electrically connecting predetermined ones of said data lines, coupled to a selected memory cell, to said common write line during a write operation and for disconnecting said common read line from said predetermined data lines during said write operation; wherein said write transfer gates are comprised of MOS transistors having a channel of a first conductivity type, said read transfer gates are comprised of MOS transistors having a channel of a second conductivity type, opposite to said first conductivity type, each electrical connection of a data line to said common write lines is effected selectively through a source-to-drain path of a MOS transistor of a corresponding transfer gate, during a write mode, in response to a column selection signal, and individual rows of memory cells are selected in response to word line selection signals corresponding thereto; and wherein at least one of said row and column decoders is comprised of: a plurality of logic gates each including a first input terminal for receiving ones of first input signals, wherein said logic gates are coupled to a common node, respectively; a first switching element coupled to said common node; a second switching element coupled to said common node, wherein said first switching element comprises an NMOS transistor, and said second switching element comprises a PMOS transistor, gates of both said NMOS transistor and said PMOS transistor are coupled to a second input terminal for receiving a second input signal which is common to said plurality of logic gates, and source-drain paths of said NMOS transistor and said PMOS transistor are coupled to said common node; and a switching circuit coupled to said common node through said source-drain path of said NMOS transistor of said first switching element, wherein said switching circuit is coupled to a third input terminal for receiving a third input signal, said third input signal together with said first input signals and said second input signal are indicative of an input address.

Claim 30

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns and coupled to word lines and data lines, each row of memory cells being associated with a respective word line and each column of memory cells being associated with at least one data line; selecting means for selecting predetermined ones of said memory cells for reading and writing operations, said selecting means including row and column decoders which are coupled to receive input signals corresponding to an X address and a Y address and which output row and column selection signals, respectively; a common write line coupled to said data lines through write transfer gates; a common read line coupled to said data lines through read transfer gates; control means coupled to said write transfer gates and to said read transfer gates for electrically connecting predetermined ones of said data lines, coupled to a selected memory cell, to said common write line during a write operation and for disconnecting said common read line from said predetermined data lines during said write operation; wherein said write transfer gates are comprised of MOS transistors having a channel of a first conductivity type, said read transfer gates are comprised of MOS transistors having a channel of a second conductivity type, opposite to said first conductivity type, each electrical connection of a data line to said common write lines is effected selectively through a source-to-drain path of a MOS transistor of a corresponding transfer gate, during a write mode, in response to a column selection signal, and individual rows of memory cells are selected in response to word line selection signals corresponding thereto; and wherein at least one of said row and column decoders is comprised of: a plurality of logic gates each including a first input terminal for receiving ones of first input signals, wherein said logic gates are coupled to a common node, respectively; a first switching element coupled to said common node; a second switching element coupled to said common node, wherein said first switching element comprises an NMOS transistor, and said second switching element comprises a PMOS transistor, gates of both said NMOS transistor and said PMOS transistor are coupled to a second input terminal for receiving a second input signal which is common to said plurality of logic gates, and source-drain paths of said NMOS transistor and said PMOS transistor are coupled to said common node; and a switching circuit coupled to said common node through said source-drain path of said NMOS transistor of said first switching element, wherein said switching circuit is coupled to a third input terminal for receiving a third input signal, said third input signal together with said first input signals and said second input signal are indicative of an input address.

Claim 31

A semiconductor memory according to claim 22, wherein said switching circuit is comprised of at least one field effect transistor and at least one bipolar transistor.

Claim 32

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns and coupled to word lines and data lines, each row of memory cells being associated with a respective word line and each column of memory cells being associated with at least one data line; selecting means for selecting predetermined ones of said memory cells for reading and writing operations, said selecting means including row and column decoders which are coupled to receive input signals corresponding to an X address and a Y address and which output row and column selection signals, respectively; a common write line coupled to said data lines through write transfer gates; a common read line coupled to said data lines through read transfer gates; control means coupled to said write transfer gates and to said read transfer gates for electrically connecting predetermined ones of said data lines, coupled to a selected memory cell, to said common write line during a write operation and for disconnecting said common read line from said predetermined data lines during said write operation; wherein said write transfer gates are comprised of MOS transistors having a channel of a first conductivity type, said read transfer gates are comprised of MOS transistors having a channel of a second conductivity type, opposite to said first conductivity type, each electrical connection of a data line to said common write lines is effected selectively through a source-to-drain path of a MOS transistor of a corresponding transfer gate, during a write mode, in response to a column selection signal, and individual rows of memory cells are selected in response to word line selection signals corresponding thereto; and wherein at least one of said row and column decoders is comprised of: a plurality of logic gates, each logic gate including a first input terminal for respectively receiving first input signals and being coupled to a common node; a first switching element coupled to said common node; and a plurality of second switching elements, coupled to said common node, provided for all of said logic gates, wherein said first switching element and said second switching elements are coupled to a second input terminal for receiving a second input signal which is common to said plurality of logic gates, and further wherein said second switching elements, in combination, operate in a manner complementary to that of said first switching element in response to said second input signal, said first input signals and said second input signal being indicative of an input address.

Claim 33

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns and coupled to word lines and data lines, each row of memory cells being associated with a respective word line and each column of memory cells being associated with at least one data line; selecting means for selecting predetermined ones of said memory cells for reading and writing operations, said selecting means including row and column decoders which are coupled to receive input signals corresponding to an X address and a Y address and which output row and column selection signals, respectively; a common write line coupled to said data lines through write transfer gates; a common read line coupled to said data lines through read transfer gates; control means coupled to said write transfer gates and to said read transfer gates for electrically connecting predetermined ones of said data lines, coupled to a selected memory cell, to said common write line during a write operation and for disconnecting said common read line from said predetermined data lines during said write operation; wherein said write transfer gates are comprised of MOS transistors having a channel of a first conductivity type, said read transfer gates are comprised of MOS transistors having a channel of a second conductivity type, opposite to said first conductivity type, each electrical connection of a data line to said common write lines is effected selectively through a source-to-drain path of a MOS transistor of a corresponding transfer gate, during a write mode, in response to a column selection signal, and individual rows of memory cells are selected in response to word line selection signals corresponding thereto; and wherein at least one of said row and column decoders is comprised of: a plurality of logic gates, each logic gate including a first input terminal for respectively receiving first input signals and being coupled to a common node; a first switching element coupled to said common node; and a plurality of second switching elements, coupled to said common node, provided for all of said logic gates, wherein said first switching element and said second switching elements are coupled to a second input terminal for receiving a second input signal which is common to said plurality of logic gates, and further wherein said second switching elements, in combination, operate in a manner complementary to that of said first switching element in response to said second input signal, said first input signals and said second input signal being indicative of an input address.

Claim 34

A semiconductor memory according to claim 24, wherein each of said logic gates includes a first MOS transistor having a gate coupled to said corresponding first input terminal and a source-drain path coupled to said common node, and a second MOS transistor having a channel region of opposite conductivity type to the conductivity type of a channel region of the first MOS transistor, said second MOS transistor having a gate coupled to said first input terminal of said logic gate and a source-drain path coupled in series between a power source potential and the source-drain path of said first MOS transistor.

Claim 35

A semiconductor memory according to claim 25, wherein said first switching element comprises a NMOS transistor, wherein said second switching elements include at least a PMOS transistor, wherein a gate of said NMOS transistor of said first switching element and a gate of said PMOS transistor of said second switching elements are respectively coupled to said second input terminal, wherein a source-drain path of said NMOS transistor of said first switching element is coupled to said common node, and wherein said NMOS transistor and said second switching elements, in combination, are respectively coupled to provide pull-down and pull-up level action at said common node in response to said second input signal.

Claim 36

A semiconductor memory according to claim 26, wherein said first MOS transistor is a NMOS transistor, and wherein said second MOS transistor is a PMOS transistor.

Claim 37

A semiconductor memory according to claim 27, further comprising a switching circuit coupled to said common node through said source-drain path of said NMOS transistor of said first switching element, wherein said switching circuit is coupled to a third input terminal for receiving a third input signal.

Claim 38

A semiconductor memory according to claim 28, wherein said third switching circuit is comprised of at least one field effect transistor and at least one bipolar transistor.

Claim 39

A semiconductor memory according to claim 25, wherein said first switching element includes a NMOS transistor and said second switching elements comprise a CMOS inverting circuit and a pull-up connected bipolar transistor, said CMOS inverting circuit having an input coupled, in common with a gate of said NMOS transistor, to receive said second input signal and having an output coupled to said pull-up connected bipolar transistor, said bipolar transistor and said NMOS transistor being series-connected across a voltage potential corresponding to an operating potential of said memory, and the common coupling of said bipolar transistor with said NMOS transistor, operating as a pull-down transistor, providing an output to said common node which operates as another, common input terminal of said plurality of logic gates.

Claim 40

A semiconductor memory according to claim 24, wherein said first switching element and said plurality of second switching elements are coupled to provide the logic invert, at said common node, of said second input signal.

Claim 41

A semiconductor memory according to claim 24, wherein said first switching element and said plurality of second switching elements constitute a BiCMOS inverter.

Claim 42

A semiconductor memory according to claim 24, wherein said first switching element includes a NMOS transistor and said second switching elements comprise a CMOS inverting circuit and a pull-up connected bipolar transistor, said CMOS inverting circuit having an input coupled, in common with a gate of said NMOS transistor, to receive said second input signal and having an output coupled to said pull-up connected bipolar transistor, said bipolar transistor and said NMOS transistor being series-connected across a voltage potential corresponding to an operating potential of said memory, and the common coupling of said bipolar transistor with said NMOS transistor, operating as a pull-down transistor, providing an output to said common node which operates as another, common input terminal of said plurality of logic gates.

Claim 43

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns and coupled to word lines and data lines, each row of memory cells being associated with a respective word line and each column of memory cells being associated with at least one data line; selecting means for selecting predetermined ones of said memory cells for reading and writing operations, said selecting means including row and column decoders which are coupled to receive input signals corresponding to an X address and a Y address and which output row and column selection signals, respectively; a common write line coupled to said data lines through write transfer gates; a common read line coupled to said data lines through read transfer gates; control means coupled to said write transfer gates and to said read transfer gates for electrically connecting predetermined ones of said data lines, coupled to a selected memory cell, to said common write line during a write operation and for disconnecting said common read line from said predetermined data lines during said write operation; wherein said write transfer gates are comprised of MOS transistors having a channel of a first conductivity type, said read transfer gates are comprised of MOS transistors having a channel of a second conductivity type, opposite to said first conductivity type, each electrical connection of a data line to said common write lines is effected selectively through a source-to-drain path of a MOS transistor of a corresponding transfer gate, during a write mode, in response to a column selection signal, and individual rows of memory cells are selected in response to word line selection signals corresponding thereto; and wherein at least one of said row and column decoders is comprised of: a plurality of logic gate each including a first input terminal for receiving ones of first input signals, said plurality of logic gates being coupled to a common node, respectively; a first switching element coupled to said common node; a second switching element coupled to said common node, said first switching element comprising an NMOS transistor and said second switching element comprising a PMOS transistor, gates of both said NMOS transistor and said PMOS transistor being coupled to a second input terminal for receiving a second input signal which is common to said plurality of logic gates, and source-drain paths of said NMOS transistor and said PMOS transistor being coupled to said common node; and a third switching element coupled to said common node through said source-drain path of said NMOS transistor of said first switching element, said third switching element being coupled to a third input terminal for receiving a third input signal, and the first through third input signals being indicative of an input address in which the second and third signals function as control signals, respectively.

Claim 44

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns and coupled to word lines and data lines, each row of memory cells being associated with a respective word line and each column of memory cells being associated with at least one data line; selecting means for selecting predetermined ones of said memory cells for reading and writing operations, said selecting means including row and column decoders which are coupled to receive input signals corresponding to an X address and a Y address and which output row and column selection signals, respectively; a common write line coupled to said data lines through write transfer gates; a common read line coupled to said data lines through read transfer gates; control means coupled to said write transfer gates and to said read transfer gates for electrically connecting predetermined ones of said data lines, coupled to a selected memory cell, to said common write line during a write operation and for disconnecting said common read line from said predetermined data lines during said write operation; wherein said write transfer gates are comprised of MOS transistors having a channel of a first conductivity type, said read transfer gates are comprised of MOS transistors having a channel of a second conductivity type, opposite to said first conductivity type, each electrical connection of a data line to said common write lines is effected selectively through a source-to-drain path of a MOS transistor of a corresponding transfer gate, during a write mode, in response to a column selection signal, and individual rows of memory cells are selected in response to word line selection signals corresponding thereto; and wherein at least one of said row and column decoders is comprised of: a plurality of logic gate each including a first input terminal for receiving ones of first input signals, said plurality of logic gates being coupled to a common node, respectively; a first switching element coupled to said common node; a second switching element coupled to said common node, said first switching element comprising an NMOS transistor and said second switching element comprising a PMOS transistor, gates of both said NMOS transistor and said PMOS transistor being coupled to a second input terminal for receiving a second input signal which is common to said plurality of logic gates, and source-drain paths of said NMOS transistor and said PMOS transistor being coupled to said common node; and a third switching element coupled to said common node through said source-drain path of said NMOS transistor of said first switching element, said third switching element being coupled to a third input terminal for receiving a third input signal, and the first through third input signals being indicative of an input address in which the second and third signals function as control signals, respectively.