Auto-verification of programming flash memory cells

Claim 2

A circuit for verifying that a flash EEPROM memory device in a flash EEPROM memory array has reached a particular programmed state comprising: means for providing a programming pulse of a preselected level and unspecified duration to the device, means for monitoring the current through the device as the programming pulse is applied, the means for monitoring the current through the device comprising: means for mirroring the current through the flash EEPROM memory device through devices selected to provide an output voltage, and means for comparing the output voltage to a reference voltage indicating a device is in the particular programmed state, and means for providing a signal to terminate the programming pulse when the current through the device reaches a state equivalent to that through a device in the desired programmed state.

Claim 3

A circuit for verifying that a flash EEPROM memory device in a flash EEPROM memory array has reached a particular programmed state as claimed in claim 1 in which the means for providing a signal to terminate the programming pulse when the current through the device reaches a state equivalent to that through a device in the desired programmed state comprises: means for sensing the output signal, and means for terminating the programming pulse when the output signal changes state.

Claim 4

A circuit for verifying that a flash EEPROM memory device in a flash EEPROM memory array has reached a particular programmed state as claimed in claim 1 in which the means for providing a programming pulse of a preselected level and unspecified duration to the device comprises means for providing a programming voltage to a bitline to which the flash EEPROM memory device is joined utilizing devices which are disabled when the state of the output signal switches.

Claim 5

A circuit for verifying that a flash EEPROM memory device in a flash EEPROM memory array has reached a particular programmed state as claimed in claim 1: in which the means for providing a signal to terminate the programming pulse when the current through the device reaches a state equivalent to that through a device in the particular programmed state comprises: means for sensing the output signal, and means for terminating the programming pulse when the output signal changes state; and in which the means for providing a programming pulse of a preselected level and unspecified duration to the device comprises means for providing a programming voltage to a bitline to which the flash EEPROM memory device is joined utilizing devices which are disabled when the state of the output signal switches.

Claim 8

A method for verifying that a flash EEPROM memory device has reached a particular state as claimed in claim 5 in which the step of providing a signal to terminate the pulse when the current through the device reaches a state equivalent to that through a device in the particular state comprises the steps of: sensing the output signal, and terminating the pulse when the output signal changes state.

Claim 9

A method for verifying that a flash EEPROM memory device has reached a particular state as claimed in claim 5 in which the step of providing a pulse of a preselected level and unspecified duration to the device comprises providing a voltage to a bitline to which the flash EEPROM memory device is joined utilizing devices which are disabled when the state of the output signal switches.

Claim 10

A method for verifying that a flash EEPROM memory device has reached a particular state as claimed in claim 5, in which the step of providing a signal to terminate the pulse when the current through the device reaches a state equivalent to that through a device in the particular state comprises the steps of: sensing an output from the sense amplifier, and terminating the pulse when the output from the sense amplifier changes state; and in which the step of providing a pulse of a preselected level and unspecified duration to the device comprises providing a voltage to a bitline to which the flash EEPROM memory device is joined utilizing devices which are disabled when the state of the output signal switches.

Claim 11

A circuit for verifying that a flash EEPROM memory device in a flash EEPROM memory array of memory devices connected in rows to wordlines and columns to bitlines has reached a particular programmed state comprising: a switching circuit for providing a pulse of a preselected level and unspecified duration to the memory device, a circuit for monitoring the current through the device as the programming pulse is applied, the circuit for monitoring the current through the device comprising: a current mirror circuit for mirroring the current through the flash EEPROM memory device including devices selected to provide an output voltage, and a sense amplifier for comparing the output voltage at one input terminal to a reference voltage indicating a device is in the particular programmed state at another input terminal, and a feedback circuit for providing a signal to terminate the programming pulse when the current through the device reaches a state equivalent to that through a device in the desired programmed state.

Claim 12

A circuit for verifying that a flash EEPROM memory device in a flash EEPROM memory array of memory devices connected in rows to wordlines and columns to bitlines has reached a particular programmed state comprising: a switching circuit for providing a pulse of a preselected level and unspecified duration to the memory device, a circuit for monitoring the current through the device as the programming pulse is applied, the circuit for monitoring the current through the device comprising: a current mirror circuit for mirroring the current through the flash EEPROM memory device including devices selected to provide an output voltage, and a sense amplifier for comparing the output voltage at one input terminal to a reference voltage indicating a device is in the particular programmed state at another input terminal, and a feedback circuit for providing a signal to terminate the programming pulse when the current through the device reaches a state equivalent to that through a device in the desired programmed state.

Claim 13

A circuit for verifying that a flash EEPROM memory device in a flash EEPROM memory array of memory devices connected in rows to wordlines and columns to bitlines has reached a particular programmed state as claimed in claim 9 in which the feedback circuit for providing a signal to terminate the programming pulse when the current through the device reaches a state equivalent to that through a device in the desired programmed state comprises: a circuit connected to sense an output of the sense amplifier and to cause the switching circuit to terminate the programming pulse when the output of the sense amplifier changes state.

Claim 14

A circuit for verifying that a flash EEPROM memory device in a flash EEPROM memory array of memory devices connected in rows to wordlines and columns to bitlines has reached a particular programmed state as claimed in claim 9 in which the switching circuit for providing a programming pulse of a preselected level and unspecified duration to the device comprises transistor devices joining a programming voltage to a bitline to which the flash EEPROM memory device is joined which transistor devices are disabled when the state of the output of the sense amplifier switches.

Claim 15

A circuit for verifying that a flash EEPROM memory device in a flash EEPROM memory array has reached a particular programmed state as claimed in claim 9: in which the feedback circuit for providing a signal to terminate the programming pulse when the current through the device reaches a state equivalent to that through a device in the desired programmed state comprises: a circuit connected to sense an output of the sense amplifier and to cause the switching circuit to terminate the programming pulse when the output of the sense amplifier changes state; and in which the switching circuit for providing a pulse of a preselected level and unspecified duration to the memory device comprises transistor devices joining a programming voltage to a bitline to which the flash EEPROM memory device is joined which transistor devices are disabled when the state of the output of the sense amplifier switches.

Claim 16

A computer system comprising: a central processing unit; an input/output bus; a bridge circuit joining the central processing unit to the input/output bus; and a flash EEPROM memory array for providing long term storage joined to the input/output bus, the flash EEPROM memory array comprising: a plurality of flash EEPROM memory devices connected in rows to wordlines and columns to bitlines, and a circuit for verifying that a flash EEPROM memory device has reached a particular programmed state comprising: a switching circuit for providing a pulse of a preselected level and unspecified duration to the memory device, a circuit for monitoring the current through the device as the programming pulse is applied, and a feedback circuit for providing a signal to terminate the programming pulse when the current through the device reaches a state equivalent to that through a device in the desired programmed state.

Claim 17

A computer system comprising: a central processing unit; an input/output bus; a bridge circuit joining the central processing unit to the input/output bus; and a flash EEPROM memory array for providing long term storage joined to the input/output bus, the flash EEPROM memory array comprising: a plurality of flash EEPROM memory devices connected in rows to wordlines and columns to bitlines, and a circuit for verifying that a flash EEPROM memory device has reached a particular programmed state comprising: a switching circuit for providing a pulse of a preselected level and unspecified duration to the memory device, a circuit for monitoring the current through the device as the programming pulse is applied, and a feedback circuit for providing a signal to terminate the programming pulse when the current through the device reaches a state equivalent to that through a device in the desired programmed state.

Claim 18

A computer system as claimed in claim 13 in which the circuit for monitoring the current through the device as the programming pulse is applied comprises: a current mirror circuit for mirroring the current through the flash EEPROM memory device including devices selected to provide an output voltage, and a sense amplifier for comparing the output voltage at one input terminal to a reference voltage indicating a device in the particular programmed state at another input terminal.

Claim 19

A computer system as claimed in claim 14 in which the feedback circuit for providing a signal to terminate the programming pulse when the current through the device reaches a state equivalent to that through a device in the desired programmed state comprises: a circuit connected to sense an output of the sense amplifier and to cause the switching circuit to terminate the programming pulse when the output of the sense amplifier changes state.

Claim 20

A computer system as claimed in claim 13 in which the switching circuit for providing a programming pulse of a preselected level and unspecified duration to the device comprises transistor devices joining a programming voltage to a bitline to which the flash EEPROM memory device is joined which transistor devices are disabled when the state of the output of the sense amplifier switches.

Claim 21

A computer system as claimed in claim 13: in which the circuit for monitoring the current through the device as the programming pulse is applied comprises: a current mirror circuit for mirroring the current through the flash EEPROM memory device including devices selected to provide an output voltage, and a sense amplifier for comparing the output voltage at one input terminal to a reference voltage indicating a device in the particular programmed state at another input terminal, and; in which the feedback circuit for providing a signal to terminate the programming pulse when the current through the device reaches a state equivalent to that through a device in the desired programmed state comprises: a circuit connected to sense an output of the sense amplifier and to cause the switching circuit to terminate the programming pulse when the output of the sense amplifier changes state; and in which the switching circuit for providing a pulse of a preselected level and unspecified duration to the memory device comprises transistor devices joining a programming voltage to a bitline to which the flash EEPROM memory device is joined which transistor devices are disabled when the state of the output of the sense amplifier switches.