US5685012A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for employing high speed data transfer between host and peripheral via host interface circuitry utilizing an IOread signal driven by the peripheral or the host
Assignee: Micron Technology Inc
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Filing: 1993-11-09
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Granted: 1997-11-04
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Expires: 2013-11-09
Abstract
Abstract A method and system for increasing the rate of data transfer between a PC-based computer and an IDE/ATA-compliant hard drive is disclosed. Synchronous data transfer is employed in a manner that retains full compatibility with the existing IDE/ATA standard.
Inventors
- 👤 Dean A. Klein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:00
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F13/00; G06F13/38; G06F13/382; G06F13/385; G06F13/42; G06F13/4265; G06F13/4269; G06F3/0602; G06F3/061; G06F3/0613; G06F3/0628; G06F3/0655; G06F3/0661; G06F3/0668; G06F3/0671; G06F3/0673; G06F3/0674; G06F3/0676
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
223 words
An apparatus for accelerating data transfer between a host computer and a peripheral, wherein the peripheral is compatible with IDE/ATA standards, said apparatus comprising: host interface circuitry that is compatible with IDE/ATA standards and that is connected to said host computer; means for requesting a first set of data to be transferred from the peripheral to the host interface; buffer means for storing the first set of data within the peripheral; communication means for communicating to the host interface that the first set of data is ready to be transferred from the peripheral; communication means for communicating to the peripheral that the first set of data is ready to be received by the host interface; means for tri-stating the IORead connection at the host interface so that the peripheral can drive the IORead connection; wherein said first set of data is transferred from the peripheral to the host interface as the peripheral asserts the IORead signal for each word of data sent from the peripheral; means for transferring the first set of data from the host interface to the host; means for requesting a second set of data to be transferred from the peripheral to the host interface; and means for transferring the second set of data from the peripheral to the host interface when the IORead signal is strobed by the host.
Claim 2
Independent Claim
223 words
An apparatus for accelerating data transfer between a host computer and a peripheral, wherein the peripheral is compatible with IDE/ATA standards, said apparatus comprising: host interface circuitry that is compatible with IDE/ATA standards and that is connected to said host computer; means for requesting a first set of data to be transferred from the peripheral to the host interface; buffer means for storing the first set of data within the peripheral; communication means for communicating to the host interface that the first set of data is ready to be transferred from the peripheral; communication means for communicating to the peripheral that the first set of data is ready to be received by the host interface; means for tri-stating the IORead connection at the host interface so that the peripheral can drive the IORead connection; wherein said first set of data is transferred from the peripheral to the host interface as the peripheral asserts the IORead signal for each word of data sent from the peripheral; means for transferring the first set of data from the host interface to the host; means for requesting a second set of data to be transferred from the peripheral to the host interface; and means for transferring the second set of data from the peripheral to the host interface when the IORead signal is strobed by the host.
Claim 3
Dependent Claim
41 words
An apparatus as claimed in claim 1, wherein said control signals further include an IOWrite signal, said apparatus further comprising: means, in the host interface circuitry, for driving said IOWrite signal and said data over said communication means to said peripheral.
Claim 4
Dependent Claim
32 words
An apparatus as claimed in claim 2, wherein said host interface circuitry includes a bi-directional FIFO buffer for use in accommodating differences in speed between the host interface circuitry and the peripheral.
Claim 5
Dependent Claim
28 words
An apparatus as claimed in claim 2, wherein said peripheral includes means for programming burst lengths, and wherein said host interface circuitry includes means for programming burst lengths.
Claim 6
Dependent Claim
17 words
An apparatus as claimed in claim 2, wherein said apparatus further comprises means for negotiating burst lengths.
Claim 7
Dependent Claim
15 words
An apparatus as claimed in claim 5, wherein said apparatus further comprises an arbitration tree.
Claim 8
Dependent Claim
30 words
An apparatus as claimed in claim 5, wherein said apparatus further comprises means for negotiating burst lengths by using an address line connecting said peripheral and said host interface circuitry.
Claim 9
Dependent Claim
17 words
An apparatus as claimed in claim 2, wherein said apparatus further comprises means for programming burst rates.
Claim 10
Dependent Claim
28 words
An apparatus as claimed in claim 2, wherein said peripheral includes means for programming burst rates, and wherein said host interface circuitry includes means for programming burst rates.
Claim 11
Dependent Claim
266 words
A computer comprising: (a) a host processing unit; (b) a bus, connected to the host processing unit; (c) host interface circuitry that is compatible with an interface protocol in which control signals are driven by the host processing unit, wherein the host interface circuitry is connected to the host processing unit by the bus, and wherein the host interface circuitry includes means for driving an IOWrite signal and data; (d) a peripheral that is compatible with an interface protocol in which control signals are driven by the host processing unit, wherein the peripheral includes means for driving an IORead signal and data; and (e) a communication medium for communicating data and control signals between the host interface circuitry and the peripheral device, wherein the control signals include the IORead signal and the IOWrite signal; wherein said host interface circuitry drives the IOWrite signal and data over the communication medium to said peripheral during write operations, and wherein said peripheral drives the IORead signal and data over the communication medium to said host interface circuitry during read operations; wherein a first set of data is transferred from the peripheral to the host interface as the peripheral asserts the IORead signal for each word of data sent from the peripheral; means for transferring the first set of data from the host interface to the host; means for requesting a second set of data to be transferred from the peripheral to the host interface; and means for transferring the second set of data from the peripheral to the host interface when the IORead signal is strobed by the host.
Claim 12
Dependent Claim
266 words
A computer comprising: (a) a host processing unit; (b) a bus, connected to the host processing unit; (c) host interface circuitry that is compatible with an interface protocol in which control signals are driven by the host processing unit, wherein the host interface circuitry is connected to the host processing unit by the bus, and wherein the host interface circuitry includes means for driving an IOWrite signal and data; (d) a peripheral that is compatible with an interface protocol in which control signals are driven by the host processing unit, wherein the peripheral includes means for driving an IORead signal and data; and (e) a communication medium for communicating data and control signals between the host interface circuitry and the peripheral device, wherein the control signals include the IORead signal and the IOWrite signal; wherein said host interface circuitry drives the IOWrite signal and data over the communication medium to said peripheral during write operations, and wherein said peripheral drives the IORead signal and data over the communication medium to said host interface circuitry during read operations; wherein a first set of data is transferred from the peripheral to the host interface as the peripheral asserts the IORead signal for each word of data sent from the peripheral; means for transferring the first set of data from the host interface to the host; means for requesting a second set of data to be transferred from the peripheral to the host interface; and means for transferring the second set of data from the peripheral to the host interface when the IORead signal is strobed by the host.
Claim 13
Dependent Claim
208 words
An interface comprising: (a) host interface circuitry that is compatible with IDE/ATA standards, and that includes means for driving an IOWrite signal and data; (b) a peripheral that is compatible with IDE/ATA standards, and that includes means for driving an IORead signal and data; and (c) a communication medium for communicating data and control signals between the host interface circuitry and the peripheral device, wherein the control signals include the IORead signal and the IOWrite signal; wherein said host interface circuitry drives the IOWrite signal and data over the communication medium to said peripheral during write operations, and wherein said peripheral drives the IORead signal and data over the communication medium to said host interface circuitry during read operations; wherein a first set of data is transferred from the peripheral to the host interface as the peripheral asserts the IORead signal for each word of data sent from the peripheral; means for transferring the first set of data from the host interface to the host; means for requesting a second set of data to be transferred from the peripheral to the host interface; and means for transferring the second set of data from the peripheral to the host interface when the IORead signal is strobed by the host.
Claim 14
Dependent Claim
208 words
An interface comprising: (a) host interface circuitry that is compatible with IDE/ATA standards, and that includes means for driving an IOWrite signal and data; (b) a peripheral that is compatible with IDE/ATA standards, and that includes means for driving an IORead signal and data; and (c) a communication medium for communicating data and control signals between the host interface circuitry and the peripheral device, wherein the control signals include the IORead signal and the IOWrite signal; wherein said host interface circuitry drives the IOWrite signal and data over the communication medium to said peripheral during write operations, and wherein said peripheral drives the IORead signal and data over the communication medium to said host interface circuitry during read operations; wherein a first set of data is transferred from the peripheral to the host interface as the peripheral asserts the IORead signal for each word of data sent from the peripheral; means for transferring the first set of data from the host interface to the host; means for requesting a second set of data to be transferred from the peripheral to the host interface; and means for transferring the second set of data from the peripheral to the host interface when the IORead signal is strobed by the host.
Claim 15
Dependent Claim
25 words
The computer of claim 10, wherein the interface protocol in which control signals are driven by the host processing unit is compatible with IDE/ATA standards.
Claim 16
Independent Claim
223 words
A method of reading data from a peripheral to a host using a host interface, wherein the host interface and the peripheral communicate over an IORead connection and a data connection, the method comprising the steps of: requesting that a first set of data be transferred from the peripheral to the host interface; negotiating a burst length that specifies the number of words that are to be transferred from the peripheral to the host interface; gathering the first set of data into a buffer within the peripheral; communicating to the host interface that the first set of data is ready to be transferred from the peripheral; communicating to the peripheral that the first set of data is ready to be received by the host interface; tri-stating the IORead connection at the host interface so that the peripheral can drive the IORead connection; transferring the first set of data from the peripheral to the host interface as the peripheral asserts the IORead signal for each word of data sent from the peripheral; transferring the first set of data from the host interface to the host; requesting that a second set of data be transferred from the peripheral to the host interface; and transferring the second set of data from the peripheral to the host interface when the IORead signal is strobed by the host.
Claim 17
Independent Claim
223 words
A method of reading data from a peripheral to a host using a host interface, wherein the host interface and the peripheral communicate over an IORead connection and a data connection, the method comprising the steps of: requesting that a first set of data be transferred from the peripheral to the host interface; negotiating a burst length that specifies the number of words that are to be transferred from the peripheral to the host interface; gathering the first set of data into a buffer within the peripheral; communicating to the host interface that the first set of data is ready to be transferred from the peripheral; communicating to the peripheral that the first set of data is ready to be received by the host interface; tri-stating the IORead connection at the host interface so that the peripheral can drive the IORead connection; transferring the first set of data from the peripheral to the host interface as the peripheral asserts the IORead signal for each word of data sent from the peripheral; transferring the first set of data from the host interface to the host; requesting that a second set of data be transferred from the peripheral to the host interface; and transferring the second set of data from the peripheral to the host interface when the IORead signal is strobed by the host.
Claim 18
Dependent Claim
16 words
The method of claim 13, wherein a word of data consists of 16 bits of information.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-03 | 2001-05-05 | 2001-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-03 | 2005-05-05 | 2005-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-03 | 2009-05-05 | 2009-11-04 | $7700.00 | Window Closed / Lapsed |