Cell generation method and cell generation system

Claim 1

A method of generating cells for a semiconductor integrated circuit, said method comprising the steps of: (a) determining locations of transistors in a cell; (b) finding wire routings between said transistors on a gridded plane; and (c) performing a compaction process on a placement/wiring result on said gridded plane; said step (a) including: (a-1) initializing a grouping of transistors, said grouping being arranged in accordance with diffusion sharing; (a-2) modifying said grouping; (a-3) finding locations of transistors in said modified grouping; (a-4) evaluating said locations found at said step (a-3); and (a-5) making a judgment of whether to accept said locations found at said step (a-3) according to said evaluation made at said step (a-4).

Claim 2

A method of generating cells for a semiconductor integrated circuit, said method comprising the steps of: (a) determining locations of transistors in a cell; (b) finding wire routings between said transistors on a gridded plane; and (c) performing a compaction process on a placement/wiring result on said gridded plane; said step (a) including: (a-1) initializing a grouping of transistors, said grouping being arranged in accordance with diffusion sharing; (a-2) modifying said grouping; (a-3) finding locations of transistors in said modified grouping; (a-4) evaluating said locations found at said step (a-3); and (a-5) making a judgment of whether to accept said locations found at said step (a-3) according to said evaluation made at said step (a-4).

Claim 6

A method of generating cells for a semiconductor integrated circuit, said method comprising the steps of: (a) determining locations of transistors in a cell; (b) finding wire routings between said transistors on a gridded plane; and (c) performing a compaction process on a placement/wiring result on said gridded plane; said step (b) including: (b-1) arranging a grid structure having a plurality of grid vertexes and a plurality of grid edges; (b-2) giving a detour wire routing length equivalent to generation of one contact; (b-3) finding a shortest distance from a starting point located at each said grid vertex to a target point; (b-4) initializing a detour distance to zero; (b-5) when no wire routings are found within a wire routing length range defined by a sum of said shortest distance and said detour distance, increasing said detour distance by one and searching an interconnection layer for a wire routing which goes through some of said plurality of grid edges from said starting point to said target point and which goes around an existing interconnection line; and (b-6) when said increased detour distance exceeds said given detour wire routing length, generating one contact and searching a different interconnection layer for a wire routing which goes through some of said plurality of grid edges from said starting point to said target point and which jumps over said existing interconnection line.

Claim 7

A method of generating cells for a semiconductor integrated circuit, said method comprising the steps of: (a) determining locations of transistors in a cell; (b) finding wire routings between said transistors on a gridded plane; and (c) performing a compaction process on a placement/wiring result on said gridded plane; said step (b) including: (b-1) arranging a grid structure having a plurality of grid vertexes and a plurality of grid edges; (b-2) giving a detour wire routing length equivalent to generation of one contact; (b-3) finding a shortest distance from a starting point located at each said grid vertex to a target point; (b-4) initializing a detour distance to zero; (b-5) when no wire routings are found within a wire routing length range defined by a sum of said shortest distance and said detour distance, increasing said detour distance by one and searching an interconnection layer for a wire routing which goes through some of said plurality of grid edges from said starting point to said target point and which goes around an existing interconnection line; and (b-6) when said increased detour distance exceeds said given detour wire routing length, generating one contact and searching a different interconnection layer for a wire routing which goes through some of said plurality of grid edges from said starting point to said target point and which jumps over said existing interconnection line.

Claim 11

A method of generating cells for a semiconductor integrated circuit, said method comprising the steps of: (a) determining locations of transistors in a cell; (b) finding wire routings between said transistors on a gridded plane; and (c) performing a compaction process on a placement/wiring result on said gridded plane; said step (c) including: (c-1) assigning inter-transistor position constraints; (c-2) finding, based on said position constraints, a cluster of transistors capable of being under-packed; (c-3) arranging a gridded plane to supreme forms of existing placement components; (c-4) shifting each transistor belonging to said cluster on said gridded plane such that each said transistor is underpacked as low as possible; (c-5) re-routing said transistors belonging to said cluster on said gridded plane; and (c-6) under-packing said transistors belonging to said cluster and interconnection lines thereof such that said transistors and said interconnection lines are under-packed as low as possible towards said existing placement components.

Claim 12

A method of generating cells for a semiconductor integrated circuit, said method comprising the steps of: (a) determining locations of transistors in a cell; (b) finding wire routings between said transistors on a gridded plane; and (c) performing a compaction process on a placement/wiring result on said gridded plane; said step (c) including: (c-1) assigning inter-transistor position constraints; (c-2) finding, based on said position constraints, a cluster of transistors capable of being under-packed; (c-3) arranging a gridded plane to supreme forms of existing placement components; (c-4) shifting each transistor belonging to said cluster on said gridded plane such that each said transistor is underpacked as low as possible; (c-5) re-routing said transistors belonging to said cluster on said gridded plane; and (c-6) under-packing said transistors belonging to said cluster and interconnection lines thereof such that said transistors and said interconnection lines are under-packed as low as possible towards said existing placement components.

Claim 15

An apparatus for generating cells for a semiconductor integrated circuit, said apparatus comprising: (a) means for determining locations of transistors in a cell; (b) means for finding wire routings between said transistors on a gridded plane; and (c) means for performing a compaction process on a placement/wiring result on said gridded plane; said means (a) including: (a-1) means for initializing a grouping of transistors, said grouping being arranged in accordance with diffusion sharing; (a-2) means for modifying said grouping; (a-3) means for finding locations of transistors in said modified grouping; (a-4) means for evaluating said locations found by said means (a-3); and (a-5) means for making a judgment of whether to accept said locations found by said means (a-3) according to said evaluation made by said means (a-4).

Claim 16

An apparatus for generating cells for a semiconductor integrated circuit, said apparatus comprising: (a) means for determining locations of transistors in a cell; (b) means for finding wire routings between said transistors on a gridded plane; and (c) means for performing a compaction process on a placement/wiring result on said gridded plane; said means (a) including: (a-1) means for initializing a grouping of transistors, said grouping being arranged in accordance with diffusion sharing; (a-2) means for modifying said grouping; (a-3) means for finding locations of transistors in said modified grouping; (a-4) means for evaluating said locations found by said means (a-3); and (a-5) means for making a judgment of whether to accept said locations found by said means (a-3) according to said evaluation made by said means (a-4).

Claim 17

An apparatus for generating cells for a semiconductor integrated circuit, said apparatus comprising: (a) means for determining locations of transistors in a cell; (b) means for finding wire routings between said transistors on a gridded plane; and (c) means for performing a compaction process on a placement/wiring result on said gridded plane; said means (b) including: (b-1) means for arranging a grid structure having a plurality of grid vertexes and a plurality of grid edges; (b-2) means for giving a detour wire routing length equivalent to generation of one contact; (b-3) means for finding a shortest distance from a starting point located at each said grid vertex to a target point; (b-4) means for initializing a detour distance to zero; (b-5) means for, when no wire routings are found within a wire routing length range defined by a sum of said shortest distance and said detour distance, increasing said detour distance by one and searching an interconnection layer for a wire routing which goes through some of said plurality of grid edges from said starting point to said target point and which goes around an existing interconnection line; and (b-6) means for, when said increased detour distance exceeds said given detour wire routing length, generating one contact and searching a different interconnection layer for a wire routing which goes through some of said plurality of grid edges from said starting point to said target point and which jumps over said existing interconnection line.

Claim 18

An apparatus for generating cells for a semiconductor integrated circuit, said apparatus comprising: (a) means for determining locations of transistors in a cell; (b) means for finding wire routings between said transistors on a gridded plane; and (c) means for performing a compaction process on a placement/wiring result on said gridded plane; said means (b) including: (b-1) means for arranging a grid structure having a plurality of grid vertexes and a plurality of grid edges; (b-2) means for giving a detour wire routing length equivalent to generation of one contact; (b-3) means for finding a shortest distance from a starting point located at each said grid vertex to a target point; (b-4) means for initializing a detour distance to zero; (b-5) means for, when no wire routings are found within a wire routing length range defined by a sum of said shortest distance and said detour distance, increasing said detour distance by one and searching an interconnection layer for a wire routing which goes through some of said plurality of grid edges from said starting point to said target point and which goes around an existing interconnection line; and (b-6) means for, when said increased detour distance exceeds said given detour wire routing length, generating one contact and searching a different interconnection layer for a wire routing which goes through some of said plurality of grid edges from said starting point to said target point and which jumps over said existing interconnection line.

Claim 19

An apparatus for generating cells for a semiconductor integrated circuit, said apparatus comprising: (a) means for determining locations of transistors in a cell; (b) means for finding wire routings between said transistors on a gridded plane; and (c) means for performing a compaction process on a placement/wiring result on said gridded plane; said means (c) including: (c-1) means for assigning inter-transistor position constraints; (c-2) means for finding, based on said position constraints, a cluster of transistors capable of being under-packed; (c-3) means for arranging a gridded plane to supreme forms of existing placement components; (c-4) means for shifting each transistor belonging to said cluster on said gridded plane such that each said transistor is under-packed as low as possible; (c-5) means for re-routing said transistors belonging to said cluster on said gridded plane; and (c-6) means for under-packing said transistors belonging to said cluster and interconnection lines thereof such that said transistors and said interconnection lines are under-packed as low as possible towards said existing placement components.

Claim 20

An apparatus for generating cells for a semiconductor integrated circuit, said apparatus comprising: (a) means for determining locations of transistors in a cell; (b) means for finding wire routings between said transistors on a gridded plane; and (c) means for performing a compaction process on a placement/wiring result on said gridded plane; said means (c) including: (c-1) means for assigning inter-transistor position constraints; (c-2) means for finding, based on said position constraints, a cluster of transistors capable of being under-packed; (c-3) means for arranging a gridded plane to supreme forms of existing placement components; (c-4) means for shifting each transistor belonging to said cluster on said gridded plane such that each said transistor is under-packed as low as possible; (c-5) means for re-routing said transistors belonging to said cluster on said gridded plane; and (c-6) means for under-packing said transistors belonging to said cluster and interconnection lines thereof such that said transistors and said interconnection lines are under-packed as low as possible towards said existing placement components.

Claim 21

A method of determining locations of transistors in a cell for a semiconductor integrated circuit, said method comprising the steps of: (a) initializing a grouping of transistors, said grouping being arranged in accordance with diffusion sharing; (b) modifying said grouping; (c) finding locations of transistors in said modified grouping; (d) evaluating said locations found at said step (c); and (e) making a judgment of whether to accept said locations found at said step (c) according to said evaluation made at said step (d).

Claim 22

A method of determining locations of transistors in a cell for a semiconductor integrated circuit, said method comprising the steps of: (a) initializing a grouping of transistors, said grouping being arranged in accordance with diffusion sharing; (b) modifying said grouping; (c) finding locations of transistors in said modified grouping; (d) evaluating said locations found at said step (c); and (e) making a judgment of whether to accept said locations found at said step (c) according to said evaluation made at said step (d).

Claim 24

A method of finding a wire routing in a semiconductor integrated circuit, said method comprising the steps of: (a) arranging a grid structure having a plurality of grid vertexes and a plurality of grid edges; (b) giving a detour wire routing length equivalent to generation of one contact; (c) finding a shortest distance from a starting point located at each said grid vertex to a target point; (d) initializing a detour distance to zero; (e) when no wire routings are found within a wire routing length range defined by a sum of said shortest distance and said detour distance, increasing said detour distance by one and searching an interconnection layer for a wire routing which goes through some of said plurality of grid edges from said starting point to said target point and which goes around an existing interconnection line; and (f) when said increased detour distance exceeds said given detour wire routing length, generating one contact and searching a different interconnection layer for a wire routing which goes through some of said plurality of grid edges from said starting point to said target point and which jumps over said existing interconnection line.

Claim 25

A method of finding a wire routing in a semiconductor integrated circuit, said method comprising the steps of: (a) arranging a grid structure having a plurality of grid vertexes and a plurality of grid edges; (b) giving a detour wire routing length equivalent to generation of one contact; (c) finding a shortest distance from a starting point located at each said grid vertex to a target point; (d) initializing a detour distance to zero; (e) when no wire routings are found within a wire routing length range defined by a sum of said shortest distance and said detour distance, increasing said detour distance by one and searching an interconnection layer for a wire routing which goes through some of said plurality of grid edges from said starting point to said target point and which goes around an existing interconnection line; and (f) when said increased detour distance exceeds said given detour wire routing length, generating one contact and searching a different interconnection layer for a wire routing which goes through some of said plurality of grid edges from said starting point to said target point and which jumps over said existing interconnection line.

Claim 27

A method of performing compaction for semiconductor integrated circuits, said method comprising the steps of: (a) assigning inter-placement component position constraints; (b) finding, based on said position constraints, a cluster of placement components capable of being under-packed; (c) arranging a gridded plane to the supreme form of existing placement components; (d) shifting each placement component belonging to said cluster on said gridded plane such that each said placement component is under-packed as low as possible; (e) re-routing said placement components belonging to said cluster on said gridded plane; and (f) under-packing said placement components belonging to said cluster and interconnection lines thereof such that said placement components and said interconnection lines are under-packed as low as possible towards said existing placement components.

Claim 28

A method of performing compaction for semiconductor integrated circuits, said method comprising the steps of: (a) assigning inter-placement component position constraints; (b) finding, based on said position constraints, a cluster of placement components capable of being under-packed; (c) arranging a gridded plane to the supreme form of existing placement components; (d) shifting each placement component belonging to said cluster on said gridded plane such that each said placement component is under-packed as low as possible; (e) re-routing said placement components belonging to said cluster on said gridded plane; and (f) under-packing said placement components belonging to said cluster and interconnection lines thereof such that said placement components and said interconnection lines are under-packed as low as possible towards said existing placement components.