Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a memory cell army having a plurality of memory cells arranged in rows and columns; a plurality of bit line pairs, each bit line pair having first and second bit lines which are connected to the memory cells in a corresponding column of said memory cell array; a plurality of sense amplifiers, each sense amplifier amplifying a potential difference between the bit lines of a corresponding one of said bit line pairs; a plurality of activation circuits for activating said plurality of sense amplifiers; a data bus for supplying input data to said plurality of memory cells; a plurality of storage circuits; each storage circuit associated with a corresponding one of the columns of said memory cell array, for storing the input data supplied from said data bus; a plurality of transfer circuits for transferring the input data stored in said storage circuits from said storage circuits to said sense amplifiers; and a transfer control circuit for controlling said plurality of transfer circuits to simultaneously transfer the input data stored in one or more of said storage circuits to said sense amplifiers; wherein said memory cell array is divided into a plurality of sub-arrays each including one or more columns of said memory cell array and at least one activation circuit is provided for each respective sub-arrays.

Claim 3

A semiconductor memory device according to claim 1, wherein each activation circuit includes a driver for driving corresponding ones of said sense amplifiers and precharging circuitry for precharging said corresponding ones of said sense amplifiers.

Claim 4

A semiconductor memory device according to claim 1, wherein each sense amplifier includes a cross-coupled type insulated gate FET pair of a first conductivity type whose drains are connected to each other and a cross-coupled type insulated gate FET pair of a second conductivity type whose drains are connected to each other; and each activation circuit includes a first circuit section for driving and precharging said insulated gate FET pair of the first conductivity type of corresponding ones of said sense amplifiers and at least some of said plurality of activation circuits each include a second circuit section for driving and precharging said insulated gate FET pair of the second conductivity type of corresponding ones of said sense amplifiers.

Claim 5

A semiconductor memory device according to claim 3, wherein the first conductivity type is an N type and the second conductivity type is a P type.

Claim 6

A semiconductor memory device according to claim 3, wherein each activation circuit includes a driver for driving said corresponding ones of said sense amplifiers and said driver includes a power supply circuit for supplying a power supply voltage to the drains of said FET pair of the second conductivity type of said corresponding ones of said sense amplifiers and supplying a reference voltage to the drains of said FET pair of the first conductivity type of said corresponding ones of said sense amplifiers.

Claim 7

A semiconductor memory device according to claim 3, wherein each activation circuit includes a precharging circuit for precharging said corresponding ones of said sense amplifiers and said precharging circuit supplies a precharge signal having a voltage equal to half the sum of the power supply voltage and the reference voltage to the drains of said FET pairs of the first and second conductivity types of said corresponding ones of said sense amplifiers.

Claim 8

A semiconductor memory device according to claim 3, wherein the number of the columns contained in each sub-array is set to a value which prevents a voltage drop occurring in the precharge signal of said activation circuits from exceeding the threshold voltage of FETs comprising said FET pair of the first conductivity type when all of the FET pairs of the first conductivity type contained in said sub-array have received the input data.

Claim 9

A semiconductor memory device according to claim 1, which further comprises a column decoder for decoding a column address signal corresponding to a column of said storage circuit in which the input data is to be stored and generating a corresponding column selection signal; and in which said transfer control circuit specifies a column in which the input data stored in said storage circuit is transferred to a corresponding one of said sense amplifiers according to the column selection signal and controls said transfer circuits to simultaneously transfer the input data to said sense amplifiers.

Claim 10

A semiconductor memory device according to claim 1, wherein said transfer control circuit controls and deactivates said transfer circuits when data is fetched from said data bus to said storage circuits.

Claim 11

A semiconductor memory device according to claim 1, further comprising column selection circuits provided between said data bus and said storage circuits and whose conduction state is controlled by a column decoder.

Claim 12

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; a plurality of word lines, each word line connected to the memory cells which are disposed in a corresponding row of said memory cell array; a plurality of bit line pairs, each bit line pair having first and second bit lines which are connected to the memory cells in a corresponding column of said memory cell array; a plurality of sense amplifiers, each sense amplifier amplifying a potential difference between the bit lines of a corresponding one of said bit line pairs; a plurality of activation circuits for activating said plurality of sense amplifiers; a data bus for supplying input data to said plurality of memory cells; a plurality of storage circuits, each storage circuit associated with a corresponding one of the columns of said memory cell array, for storing the input data supplied from said data bus; a plurality of transfer circuits for transferring the input data stored in said storage circuits from said storage circuits to said sense amplifiers; and a transfer control circuit for controlling said plurality of transfer circuits to simultaneously transfer the input data stored in one or more of said storage circuits to said sense amplifiers; wherein said memory cell array is divided into a plurality of sub-arrays each including one or more columns of said memory cell array, each of said plurality of sub-arrays and its corresponding sense amplifiers are formed in a respective area, and at least one activation circuit is provided for each respective sub-arrays and each activation circuit is formed at least partly in an area disposed between an adjacent two of said respective areas.

Claim 13

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; a plurality of word lines, each word line connected to the memory cells which are disposed in a corresponding row of said memory cell array; a plurality of bit line pairs, each bit line pair having first and second bit lines which are connected to the memory cells in a corresponding column of said memory cell array; a plurality of sense amplifiers, each sense amplifier amplifying a potential difference between the bit lines of a corresponding one of said bit line pairs; a plurality of activation circuits for activating said plurality of sense amplifiers; a data bus for supplying input data to said plurality of memory cells; a plurality of storage circuits, each storage circuit associated with a corresponding one of the columns of said memory cell array, for storing the input data supplied from said data bus; a plurality of transfer circuits for transferring the input data stored in said storage circuits from said storage circuits to said sense amplifiers; and a transfer control circuit for controlling said plurality of transfer circuits to simultaneously transfer the input data stored in one or more of said storage circuits to said sense amplifiers; wherein said memory cell array is divided into a plurality of sub-arrays each including one or more columns of said memory cell array, each of said plurality of sub-arrays and its corresponding sense amplifiers are formed in a respective area, and at least one activation circuit is provided for each respective sub-arrays and each activation circuit is formed at least partly in an area disposed between an adjacent two of said respective areas.

Claim 14

A semiconductor memory device according to claim 11, further comprising a plurality of bypass word lines respectively formed for said plurality of word lines and insulated from said plurality of word lines, wherein said bypass word lines are connected to said word lines in an area disposed between said separated areas.

Claim 15

A semiconductor memory device according to claim 11, wherein each sense amplifier includes a cross-coupled type insulated gate FET pair of a first conductivity type whose drains are connected to each other and a cross-coupled type insulated gate FET pair of a second conductivity type whose drains are connected to each other; and each activation circuit includes a first circuit section for driving and precharging said insulated gate FET pair of the first conductivity type of corresponding ones of said sense amplifiers and at least some of said plurality of activation circuits each include a second circuit section for driving and precharging said insulated gate FET pair of the second conductivity type of corresponding ones of said sense amplifiers.

Claim 16

A semiconductor memory device according to claim 13, wherein the first conductivity type is an N type and the second conductivity type is a P type.

Claim 17

A semiconductor memory device according to claim 13, wherein each activation circuit includes a driver for driving said corresponding ones of said sense amplifiers and said driver includes a power supply circuit for supplying a power supply voltage to the drain of said FET pair of the second conductivity type of said corresponding ones of said sense amplifiers and supplying a reference voltage to the drain of said FET pair of the first conductivity type of said corresponding ones of said sense amplifiers.

Claim 18

A semiconductor memory device according to claim 13, wherein each activation circuit includes a precharging circuit for precharging said corresponding ones of said sense amplifiers and said precharging circuit supplies a precharge signal having a voltage equal to half the sum of the power supply voltage and the reference voltage to the drains of said FET pairs of the first and second conductivity types of said corresponding ones of said sense amplifiers.

Claim 19

A semiconductor memory device according to claim 13, wherein the number of the columns contained in each sub-array is set to a value which prevents a voltage drop occurring in the precharge signal of said activation circuits from exceeding the threshold voltage of FETs comprising said FET pair of the first conductivity type when all of the FET pairs of the first conductivity type contained in said sub-array have received the input data.

Claim 20

A semiconductor memory device according to claim 11, which further comprises a column decoder for decoding a column address signal corresponding to a column of said storage circuit in which the input data is to be stored and generating a column selection signal; and in which said transfer control circuit specifies a column in which the input data stored in said storage circuit is transferred to a corresponding one of said sense amplifiers according to the column selection signal and controls said transfer circuits to simultaneously transfer the input data to said sense amplifiers.

Claim 21

A semiconductor memory device according to claim 11, wherein said transfer control circuit controls and deactivates said transfer circuits when data is fetched from said data bus to said storage circuits.

Claim 22

A semiconductor memory device according to claim 11, further comprising column selection circuits provided between said data bus and said storage circuits and whose conduction state is controlled by a column decoder.

Claim 23

A semiconductor memory device according to claim 1, wherein said sense amplifiers comprise latch type sense amplifiers.

Claim 24

A semiconductor memory device according to claim 1, wherein said storage circuits comprise latch type storage circuits.

Claim 25

A semiconductor memory device according to claim 11, wherein said sense amplifiers comprise latch type sense amplifiers.

Claim 26

A semiconductor memory device according to claim 11, wherein said storage circuits comprise latch type storage circuits.