US5708843A
Expired / Lapsed
US
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Method and apparatus for handling code segment violations in a computer system
Assignee: Intel Corp
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Filing: 1995-10-18
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Granted: 1998-01-13
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Expires: 2015-10-18
Abstract
Abstract A memory operation is issued in a processor. Upon detecting both that the memory operation produces a code segment violation and that the memory operation is blocked at retirement, a blocking signal is produced to block a bus access responsive to the memory operation. A second signal signifies that the memory operation completed.
Inventors
- 👤 Jeffrey M. Abramson
- 👤 Haitham Akkary
- 👤 Andrew F. Glew
- 👤 Glenn J. Hinton
- 👤 Kris G. Konigsfeld
- 👤 Rohit Vidwans
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:55
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3865; G06F9/30003; G06F9/3004; G06F9/30043; G06F9/3824; G06F9/3854; G06F9/3856; G06F9/3858; G06F9/38585
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
82 words
An apparatus for handling code segment violations in a pipelined processor comprising: detection logic that provides one or more code segment violation detection signals; circuitry that provides a blocked-at-retirement signal; and combinatorial logic responsive to the one or more code segment violation detection signals and the blocked-at-retirement signal that provides a block signal which blocks a bus access from occurring in response to a memory operation, the combinatorial logic also providing a data valid signal which indicates the memory operation has completed.
Claim 2
Independent Claim
82 words
An apparatus for handling code segment violations in a pipelined processor comprising: detection logic that provides one or more code segment violation detection signals; circuitry that provides a blocked-at-retirement signal; and combinatorial logic responsive to the one or more code segment violation detection signals and the blocked-at-retirement signal that provides a block signal which blocks a bus access from occurring in response to a memory operation, the combinatorial logic also providing a data valid signal which indicates the memory operation has completed.
Claim 3
Dependent Claim
13 words
The apparatus of claim 1 wherein the combinatorial logic comprises an AND gate.
Claim 4
Dependent Claim
21 words
The apparatus of claim 1 wherein the pipelined processor comprises a reorder buffer which includes the code segment violation detection logic.
Claim 5
Dependent Claim
38 words
The apparatus of claim 1 further wherein the pipelined processor further comprises a data cache unit, with the block signal being coupled to the data cache unit and the data valid signal being coupled to the reorder buffer.
Claim 6
Dependent Claim
130 words
A processor comprising: a reorder buffer which maintains a sequential listing of micro-operations, the reorder buffer providing one or more code segment violation signals; a data cache unit; a memory order buffer, the one or more code segment violation signals being coupled to the memory order buffer and combined with an at-retirement signal to provide a first intermediate signal, the first intermediate signal being logically ORed with other blocking signals to provide a second intermediate signal, the first intermediate result also being logically ORed with a write-back valid signal to provide a third intermediate signal, the second intermediate signal being coupled to the data cache unit to selectively disable bus requests, and the third intermediate signal being coupled to the reorder buffer to indicate that a memory operation has completed.
Claim 7
Dependent Claim
130 words
A processor comprising: a reorder buffer which maintains a sequential listing of micro-operations, the reorder buffer providing one or more code segment violation signals; a data cache unit; a memory order buffer, the one or more code segment violation signals being coupled to the memory order buffer and combined with an at-retirement signal to provide a first intermediate signal, the first intermediate signal being logically ORed with other blocking signals to provide a second intermediate signal, the first intermediate result also being logically ORed with a write-back valid signal to provide a third intermediate signal, the second intermediate signal being coupled to the data cache unit to selectively disable bus requests, and the third intermediate signal being coupled to the reorder buffer to indicate that a memory operation has completed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-12 | 2001-07-14 | 2002-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-12 | 2005-07-14 | 2006-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-12 | 2009-07-14 | 2010-01-13 | $7700.00 | Window Closed / Lapsed |