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US5709805A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for producing multi-layer circuit board and resulting article of manufacture

Assignee: International Business Machines Corp
•
Filing: 1996-11-20
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Granted: 1998-01-20
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Expires: 2016-11-20
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Abstract

Abstract A method for producing a panel of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of coating a circuitized core material that has been cut into panels with a dielectric material and copper cover sheets; forming circuits from the cover sheets by etching; applying an adhesive polymer across the dielectric material covering the entire area of the panel; applying a cover sheet; drilling the panel to form through-holes and vias; seeding and plating the through-holes and vias with joining metal; applying photo-resist to the panels exposed with an image of the area of the panel to be joined and developed; and etching the cover sheet and the photo-resist away in the area of the panel to be joined to expose the adhesive polymer.

Inventors

  • 👤 Charles Robert Davis
  • 👤 Thomas P. Gall

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 12:52
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/44; H05K3/445; H05K3/38; H05K3/386; H05K3/46; H05K3/4611; H05K3/4623; H05K3/4641; H05K1/00; H05K1/02; H05K1/03; H05K1/05; H05K1/056; H05K2201/00; H05K2201/01; H05K2201/0137; H05K2201/015; H05K2201/0183; H05K2201/0195; H05K2201/02; H05K2201/0203; H05K2201/0206; H05K2201/0209; H05K2201/03; H05K2201/0332; H05K2201/0335; H05K2201/0355; H05K2201/06; H05K2201/068; H05K3/0011; H05K3/0017; H05K3/002; H05K3/30; H05K3/303; H05K3/305; H05K3/40; H05K3/42; H05K3/425; H05K3/427; H05K3/429; H05K3/4626; Y; Y10; Y10S; Y10S428/00; Y10S428/901; Y10T; Y10T428/00; Y10T428/24; Y10T428/24802; Y10T428/24917; Y10T428/249921; Y10T428/249953; Y10T428/249982; Y10T428/249984; Y10T428/249986; Y10T428/28; Y10T428/2804; Y10T428/31504; Y10T428/3154

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 95 words
A method for producing a panel of a multi-layer electronic circuit package, comprising the steps of: selecting, circuitizing, and coating a core material with dielectric material and metal sheets on an outer surface of the core material; forming circuits on the surface of the core material; selecting and applying an adhesive polymer over the entire area of the panel; applying a cover sheet; drilling the panel and plating through-holes and vias; and applying photoresist, and selectively etching away the cover sheet in areas of the panel to be joined, to selectively expose the adhesive polymer.
Claim 2
Independent Claim 95 words
A method for producing a panel of a multi-layer electronic circuit package, comprising the steps of: selecting, circuitizing, and coating a core material with dielectric material and metal sheets on an outer surface of the core material; forming circuits on the surface of the core material; selecting and applying an adhesive polymer over the entire area of the panel; applying a cover sheet; drilling the panel and plating through-holes and vias; and applying photoresist, and selectively etching away the cover sheet in areas of the panel to be joined, to selectively expose the adhesive polymer.
Claim 3
Dependent Claim 11 words
The method of claim 1, wherein the core material is copper-Invar-copper.
Claim 4
Dependent Claim 43 words
The method of claim 1, wherein the step of circuitizing the panel further comprises: applying a photo resist or plating mask to the panel so that some part of the core material will be unplated and suitable for use for direct chip attach.
Claim 5
Dependent Claim 28 words
The method of claim 1, wherein the step of circuitizing the panel further comprises: plating the panel with copper to a plating thickness of 5 to 7 microns.
Claim 6
Dependent Claim 21 words
The method of claim 1, wherein the dielectric material used to coat the core material is a silica filled poly(tetrafluoroethylene) composite.
Claim 7
Dependent Claim 28 words
The method of claim 1, wherein the step of coating the core material with dielectric material further comprises: applying the dielectric material to both sides of the panel.
Claim 8
Dependent Claim 12 words
The method of claim 1, wherein the adhesive polymer is poly(tetrafluoroethylene-perfluorovinyl ether).
Claim 9
Dependent Claim 25 words
The method of claim 1, wherein the step of applying the adhesive polymer further comprising: applying the adhesive polymer to both sides of the panel.
Claim 10
Dependent Claim 14 words
The method of claim 1, wherein the cover sheet is of a copper material.
Claim 11
Dependent Claim 25 words
The method of claim 1, wherein the step of applying a cover sheet further comprises: applying a cover sheet to each side of the panel.
Claim 12
Dependent Claim 50 words
The method of claim 1, wherein the step of drilling the panel and plating through-holes and vias further comprises: seeding the surface of at least one cover sheet with a catalyst using via wet seeding with palladium tin; and plating the through-holes and vias using an electrically conductive metal material.
Claim 13
Dependent Claim 24 words
The method of claim 1, wherein the material used for plating through-holes and vias is selected form a group comprising copper, gold, or tin.
Claim 14
Independent Claim 96 words
A method for producing a multi-layer electronic circuit package composed of a plurality of panels, comprising the steps of: preparing each panel by selecting, circuitizing, and coating a core material with dielectric material; selecting and applying an adhesive polymer over the entire area of the panel; applying a cover sheet; drilling the panel and plating through-holes and vias applying photoresist, and selectively etching away the cover sheet in areas of the panel to be joined, to selectively expose the adhesive polymer and laminating a plurality of prepared panels together to form a multi-layer electronic circuit package.
Claim 15
Independent Claim 96 words
A method for producing a multi-layer electronic circuit package composed of a plurality of panels, comprising the steps of: preparing each panel by selecting, circuitizing, and coating a core material with dielectric material; selecting and applying an adhesive polymer over the entire area of the panel; applying a cover sheet; drilling the panel and plating through-holes and vias applying photoresist, and selectively etching away the cover sheet in areas of the panel to be joined, to selectively expose the adhesive polymer and laminating a plurality of prepared panels together to form a multi-layer electronic circuit package.
Claim 16
Independent Claim 94 words
A method for producing a panel of a multi-layer electronic circuit package comprising the steps of: selecting a core material, circuitizing the core material, and coating the circuitized core material on both sides with a dielectric material called silica filled poly(tetrafluoroethylene) composite; applying a coating of poly(tetrafluoroethylene-perfluorovinyl ether) to both sides of the panel over the entire area of the panel; drilling the panel and plating through-holes and vias; and applying photoresist and selectively etching away the coversheet in areas of the panel to be joined to selectively expose the coating of poly(tetrafluoroethylene-perfluoro-vinyl ether).
Claim 17
Independent Claim 94 words
A method for producing a panel of a multi-layer electronic circuit package comprising the steps of: selecting a core material, circuitizing the core material, and coating the circuitized core material on both sides with a dielectric material called silica filled poly(tetrafluoroethylene) composite; applying a coating of poly(tetrafluoroethylene-perfluorovinyl ether) to both sides of the panel over the entire area of the panel; drilling the panel and plating through-holes and vias; and applying photoresist and selectively etching away the coversheet in areas of the panel to be joined to selectively expose the coating of poly(tetrafluoroethylene-perfluoro-vinyl ether).

References Cited (Backward Citations)

US5153986A Cited
US5582745A Cited
US5284548A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-01-19 2001-07-21 2002-01-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-01-19 2005-07-21 2006-01-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-01-19 2009-07-21 2010-01-20 $7700.00 Window Closed / Lapsed

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