US5714766A
Expired / Lapsed
US
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Nano-structure memory device
Assignee: GlobalFoundries Inc
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Filing: 1995-09-29
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Granted: 1998-02-03
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Expires: 2015-09-29
Abstract
Abstract A memory device and memory incorporating a plurality of the memory devices is described wherein each memory device has spaced apart source and drain regions, a channel, a barrier insulating layer, a nanocrystal or a plurality of nanocrystals, a control barrier layer, and a gate electrode. The nanocrystal which may be a quantum dot, stores one electron or hole or a discrete number of electrons or holes at room temperature to provide threshold voltage shifts in excess of the thermal voltage for each change in an electron or a hole stored. The invention utilizes Coulomb blockade in electrostatically coupling one or more stored electrons or holes to a channel while avoiding in-path Coulomb-blockade controlled conduction for sensing the stored charge.
Inventors
- 👤 Wei Chen
- 👤 Theoren Perlee Smith, III
- 👤 Sandip Tiwari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 02:15
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/688; B; B82; B82Y; B82Y10/00; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5642; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; H10D30/01; H10D30/021; H10D30/0411; H10D30/687; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/832; G11C2216/00; G11C2216/02; G11C2216/08; Y; Y10; Y10S; Y10S438/00; Y10S438/962
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
77 words
A memory cell for storing k electrons or holes, where k is an integer zero or greater, indicative of data comprising: a semiconductor channel, a first insulator layer formed on said semiconductor channel, a first nanocrystal formed on said first insulator layer, said first nanocrystal electrically floating and capacitively coupled to said semiconductor channel by way of Coulomb blockade, a second insulator layer over said first nanocrystal, and a gate electrode formed on said second insulator layer.
Claim 2
Dependent Claim
77 words
A memory cell for storing k electrons or holes, where k is an integer zero or greater, indicative of data comprising: a semiconductor channel, a first insulator layer formed on said semiconductor channel, a first nanocrystal formed on said first insulator layer, said first nanocrystal electrically floating and capacitively coupled to said semiconductor channel by way of Coulomb blockade, a second insulator layer over said first nanocrystal, and a gate electrode formed on said second insulator layer.
Claim 3
Dependent Claim
18 words
The memory cell of claim 1 further including a circuit for sensing the conduction of said semiconductor channel.
Claim 4
Dependent Claim
31 words
The memory cell of claim 1 further including a circuit for detecting the presence of electrical current in said channel at times a predetermined voltage is applied to said gate electrode.
Claim 5
Dependent Claim
20 words
The memory cell of claim 3 further including a circuit for amplifying and measuring the current passing through said channel.
Claim 6
Dependent Claim
17 words
The memory cell of claim 1 further including a source region on one side of said channel.
Claim 7
Dependent Claim
26 words
The memory cell of claim 5 further including a drain region on the other side of said channel wherein said channel is below said gate electrode.
Claim 8
Dependent Claim
14 words
The memory cell of claim 1 wherein said first nanocrystal is a quantum dot.
Claim 9
Dependent Claim
47 words
The memory cell of claim 1 wherein said semiconductor channel, said first insulator layer, said first nanocrystal and second insulator have dimensions to provide a threshold voltage shift for each electron or hole stored therein equal to or greater than the threshold voltage shift for thermal voltage.
Claim 10
Dependent Claim
23 words
The memory cell of claim 1 further including a plurality of first nanocrystals spaced apart from one another on said first insulator layer.
Claim 11
Dependent Claim
16 words
The memory cell of claim 9 wherein said plurality of nanocrystals are arranged in an array.
Claim 12
Dependent Claim
14 words
The memory cell of claim 10 wherein said array is a one dimensional array.
Claim 13
Dependent Claim
14 words
The memory cell of claim 10 wherein said array is a two dimensional array.
Claim 14
Dependent Claim
37 words
The memory cell of claim 1 further including a plurality of first nanocrystals spaced apart from one another in an insulator material to form a three dimensional array of said first nanocrystals on said first insulator layer.
Claim 15
Dependent Claim
37 words
The memory cell of claim 1 wherein said first and second insulator layers are of a dielectric material selected from the group consisting of silicon oxide, silicon nitride, calcium fluoride, gallium aluminum arsenide, and gallium indium arsenide.
Claim 16
Dependent Claim
21 words
The memory cell of claim 1 wherein said first and second insulator layers are silicon oxide and said nanocrystal is silicon.
Claim 17
Dependent Claim
32 words
The memory cell of claim 1 wherein said first and second insulators are of a wider band gap material than the band gap of gallium arsenide and said nanocrystal is gallium arsenide.
Claim 18
Dependent Claim
26 words
The memory cell of claim 16 wherein said first and second insulators are selected from the group consisting of gallium aluminum arsenide and gallium indium arsenide.
Claim 19
Dependent Claim
29 words
The memory cell of claim 1 wherein said nanocrystal is a material selected from the group consisting of silicon, silicon germanium, germanium, silicon carbide, gallium arsenide and indium arsenide.
Claim 20
Dependent Claim
119 words
A memory cell for storing k electrons or holes, where k is an integer zero or greater, indicative of data comprising: a semiconductor channel, a first insulator layer formed on said semiconductor channel, a first nanocrystal formed on said first insulator layer, said first nanocrystal electrically floating and capacitively coupled to said semiconductor channel with Coulomb blockade energy, greater than the thermal voltage; a second insulator layer over said first nanocrystal, a second nanocrystal formed on said second insulator layer, said second nanocrystal electrically floating and capacitively coupled to said semiconductor channel with Coulomb blockade energy, greater than the thermal voltage; a third insulator layer over said second nanocrystal, and a gate electrode formed on said third insulator layer.
Claim 21
Dependent Claim
119 words
A memory cell for storing k electrons or holes, where k is an integer zero or greater, indicative of data comprising: a semiconductor channel, a first insulator layer formed on said semiconductor channel, a first nanocrystal formed on said first insulator layer, said first nanocrystal electrically floating and capacitively coupled to said semiconductor channel with Coulomb blockade energy, greater than the thermal voltage; a second insulator layer over said first nanocrystal, a second nanocrystal formed on said second insulator layer, said second nanocrystal electrically floating and capacitively coupled to said semiconductor channel with Coulomb blockade energy, greater than the thermal voltage; a third insulator layer over said second nanocrystal, and a gate electrode formed on said third insulator layer.
Claim 22
Dependent Claim
38 words
The memory cell of claim 19 wherein said first, second and third insulator layers are of a dielectric material selected from the group consisting of silicon oxide, silicon nitride, calcium fluoride, gallium aluminum arsenide and gallium indium arsenide.
Claim 23
Dependent Claim
25 words
The memory cell of claim 19 wherein said fist, second and third insulator layers are silicon oxide and said first and second nanocrystals are silicon.
Claim 24
Dependent Claim
36 words
The memory cell of claim 19 wherein said first, second and third insulators are of a wider band gap material than the band gap of gallium arsenide and said first and second nanocrystals are gallium arsenide.
Claim 25
Dependent Claim
27 words
The memory cell of claim 22 wherein said first, second and third insulators are selected from the group consisting of gallium aluminum arsenide and gallium indium arsenide.
Claim 26
Dependent Claim
32 words
The memory cell of claim 19 wherein said first and second nanocrystals include a material selected from the group consisting of silicon, silicon germanium, germanium, silicon carbide, gallium arsenide and indium arsenide.
Claim 27
Dependent Claim
24 words
The memory cell of claim 19 further including a first plurality of first nanocrystals spaced apart from one another on said first insulator layer.
Claim 28
Dependent Claim
23 words
The memory cell of claim 25 further including a second plurality of nanocrystals spaced apart from one another on said second insulator layer.
Claim 29
Dependent Claim
45 words
The memory cell of claim 26 further including a third plurality of third nanocrystals spaced apart from one another on a fourth insulator layer, said fourth insulator and said plurality of third nanocrystals positioned between said plurality of second nanocrystals and said third insulator layer.
Claim 30
Dependent Claim
131 words
A memory comprising: a plurality of storage devices for storing electrons or holes, each said device having a gate electrode, source region, drain region, channel, a barrier insulator layer above said channel, a nanocrystal above said barrier insulator layer, a control insulator layer above said nanocrystal, and said gate electrode on said control insulator layer, said plurality of storage devices arranged in rows and columns, said gate electrode of each storage device in each respective row coupled together and to a word line decoder, said source region of each storage device in each respective column coupled together and to a bitline decoder, and said drain region of each storage device in each respective column coupled together and to an input of a sense amplifier for sensing the data on its input.
Claim 31
Dependent Claim
131 words
A memory comprising: a plurality of storage devices for storing electrons or holes, each said device having a gate electrode, source region, drain region, channel, a barrier insulator layer above said channel, a nanocrystal above said barrier insulator layer, a control insulator layer above said nanocrystal, and said gate electrode on said control insulator layer, said plurality of storage devices arranged in rows and columns, said gate electrode of each storage device in each respective row coupled together and to a word line decoder, said source region of each storage device in each respective column coupled together and to a bitline decoder, and said drain region of each storage device in each respective column coupled together and to an input of a sense amplifier for sensing the data on its input.
Claim 32
Dependent Claim
21 words
The memory of claim 28 further including a plurality of nanocrystals spaced apart from one another on said barrier insulator layer.
Claim 33
Dependent Claim
33 words
The memory of claim 28 further including a plurality of nanocrystals spaced apart from one another in an insulator material to form a three dimensional array of nanocrystals on said barrier insulator layer.
Claim 34
Dependent Claim
39 words
The memory of claim 28 wherein said barrier insulator layer and said control insulator layer are of a dielectric material selected from the group consisting of silicon oxide, silicon nitride, calcium fluoride, gallium aluminum arsenide and gallium indium arsenide.
Claim 35
Dependent Claim
23 words
The memory of claim 28 wherein said barrier insulator layer and said control insulator layer are silicon oxide and said nanocrystal is silicon.
Claim 36
Dependent Claim
35 words
The memory of claim 28 wherein said barrier insulator layer and said control insulator layer are of a wider band gap material than the band gap of gallium arsenide and said nanocrystal is gallium arsenide.
Claim 37
Dependent Claim
29 words
The memory of claim 33 wherein said barrier insulator layer and said control insulator layer are selected from the group consisting of gallium aluminum arsenide and gallium indium arsenide.
Claim 38
Dependent Claim
28 words
The memory of claim 28 wherein said nanocrystal is a material selected from the group consisting of silicon, silicon germanium, germanium, silicon carbide, gallium arsenide and indium arsenide.
Claim 39
Dependent Claim
137 words
A memory comprising: a plurality of storage devices for storing electrons or holes, each said device having a gate electrode, source region, drain region, channel, a barrier insulator layer above said channel, a nanocrystal above said barrier insulator layer, a control insulator layer above said nanocrystal, and said gate electrode on said control insulator layer, said plurality of storage devices arranged in rows and columns, said gate electrode of each storage device in each respective row coupled together and to a word line decoder, said source region of each storage device in each respective column coupled together and to an input of a column decoder, said drain region of each storage device in each respective column coupled together and to an input of said column decoder, and an amplifier coupled to said column decoder for sensing data.
Claim 40
Dependent Claim
137 words
A memory comprising: a plurality of storage devices for storing electrons or holes, each said device having a gate electrode, source region, drain region, channel, a barrier insulator layer above said channel, a nanocrystal above said barrier insulator layer, a control insulator layer above said nanocrystal, and said gate electrode on said control insulator layer, said plurality of storage devices arranged in rows and columns, said gate electrode of each storage device in each respective row coupled together and to a word line decoder, said source region of each storage device in each respective column coupled together and to an input of a column decoder, said drain region of each storage device in each respective column coupled together and to an input of said column decoder, and an amplifier coupled to said column decoder for sensing data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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