Autonomous high speed linear space address mode translation for use with a computer hard disc system

Claim 2

A translator unit for autonomously translating between linear address spaces, wherein said address spaces are associated with a hard disc storage unit, addressable in terms of cylinder, head, and sector numbers, or a sequential logical block address is used to store data for use by a host central processor unit (CPU), comprising: a decoder for decoding bits present in commands issued by said host computer CPU, wherein different combinations of decoded said bits are associated with different modes of address translation; an algorithmic function generator for providing a set of real-time translation functions including at least (a) logical block address to logical cylinder-head-sector address mode conversion, and (b) physical cylinder-head-sector address to physical block address mode conversion; a mode selector, coupled to send algorithmic function generator, for selecting a chosen one from said set of translation functions in response to the decoded said bits; wherein said algorithmic function generator translates address space associated with said commands in response to the decoded said bits; said generator using an equation given by: X/Y=t0+r0 t0/Z=t1+r1 t1+W=r2 where X is said block address, Y is a physical sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone.

Claim 3

The translator unit of claim 1, wherein said address spaces are associated with a hard disc controller unit buffer.

Claim 4

The translator unit of claim 1, wherein said algorithmic function means translates said address space using hardware selected from the group consisting of (a) a state machine, (b) a microcontroller, and (c) a local microprocessor associated with said translator unit.

Claim 5

The translator unit of claim 1, wherein said algorithmic function means further provides at least one additional function selected from the group consisting of (c) division, and (d) multiplication.

Claim 6

A translator unit for autonomously translating between linear address spaces, wherein said address spaces are associated with a hard disc storage unit, addressable in terms of cylinder, head and sector numbers, or a sequential logical block address used to store data for use by a host central processor unit (CPU), comprising: a decoder for decoding bits present in commands issued by said host computer CPU, wherein different combinations of decoded said bits are associated with different modes of address translation; an algorithmic function generator for providing a set of real-time translation functions including at least (a) logical block address to logical cylinder-head-sector address mode conversion, and (b) physical cylinder-head-sector address to physical block address mode conversion; a mode selector coupled to said algorithmic function generator, for selecting a chosen one from said set of translation functions in response to the decoded said bits; wherein said algorithmic function generator translates address space associated with said commands in response to the decoded said bits; said generator using an equation given by: X/Y=t0+r0 t0/Z=t1+r1 t1+W=r2 where X is said block address, Y is a physical sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone; said algorithmic function generator translating a cylinder-head-sector address to a block address using an equation given by: block address=((((C*Nh)+H)*Ns)+S-1) where C is a head number, Nh is a head and drive number, H is a head number, Ns is a sector and track number, and S is a sector number.

Claim 7

A translator unit for autonomously translating between linear address spaces, wherein said address spaces are associated with a hard disc storage unit, addressable in terms of cylinder, head and sector numbers, or a sequential logical block address used to store data for use by a host central processor unit (CPU), comprising: a decoder for decoding bits present in commands issued by said host computer CPU, wherein different combinations of decoded said bits are associated with different modes of address translation; an algorithmic function generator for providing a set of real-time translation functions including at least (a) logical block address to logical cylinder-head-sector address mode conversion, and (b) physical cylinder-head-sector address to physical block address mode conversion; a mode selector coupled to said algorithmic function generator, for selecting a chosen one from said set of translation functions in response to the decoded said bits; wherein said algorithmic function generator translates address space associated with said commands in response to the decoded said bits; said generator using an equation given by: X/Y=t0+r0 t0/Z=t1+r1 t1+W=r2 where X is said block address, Y is a physical sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone; said algorithmic function generator translating a cylinder-head-sector address to a block address using an equation given by: block address=((((C*Nh)+H)*Ns)+S-1) where C is a head number, Nh is a head and drive number, H is a head number, Ns is a sector and track number, and S is a sector number.

Claim 8

A translator unit for autonomously translating between linear address spaces wherein said address spaces are associated with a hard disc storage unit addressable in terms of cylinder, head, and sector numbers, or a sequential logical block address used to store data for use by a host central processor unit (CPU), comprising: a decoder for decoding bits present in commands issued by said host computer CPU, wherein different combinations of decoded said bits are associated with different modes of address translation; an algorithmic function generator for providing a set of real-time translation functions including at least (a) logical block address to logical cylinder-head-sector address mode conversion, and (b) physical cylinder-head-sector address to physical block address mode conversion; a mode selector, coupled to said algorithmic function generator for selecting a chosen one from said set of translation functions in response to the decoded said bits; wherein said algorithmic function generator translates address space associated with said commands in response to the decoded said bits; said generator using an equation given by: X/Y=t0+r0 t0/Z=t1+r1 t1+W=r2 where X is said block address, Y is a physical sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone; means for testing whether the host CPU has written a command; a DONE register for testing whether said translator unit is presently available for translation; means for branching, in response to an output from said means for decoding, to a portion of said algorithmic function generator providing a real-time translation function corresponding to an output of said decoder; means for confirming that a host CPU command has been received, and if affirmative, means for reading task registers associated with said host CPU; wherein if said decoder determines that a multiplication function is required, said algorithmic function generator provides a multiplication function; wherein if said decoder determines that a division function is required, said algorithmic function generator provides a division function; wherein if said decoder determines that a said block address is to be converted to a cylinder-head-sector address said algorithmic function generator uses an equation given by: X/Y=t0+r0 t0/Z=t1+r1 t1+W=r2 where X is said block address, Y is a sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone; wherein if said decoder determines that a said cylinder-head-sector address is to be converted to a block address, said translator unit confirms receipt of said host CPU command and reads said task registers associated with said host CPU, and converts said address using an equation given by: block address=((((C*Nh)+H)*Ns)+S-1) where C is a head number, Nh is a head and drive number, H is a head number, Ns is a sector and track number, and S is a sector number; and means for setting said DONE register means upon translation completion.

Claim 9

A translator unit for autonomously translating between linear address spaces wherein said address spaces are associated with a hard disc storage unit addressable in terms of cylinder, head, and sector numbers, or a sequential logical block address used to store data for use by a host central processor unit (CPU), comprising: a decoder for decoding bits present in commands issued by said host computer CPU, wherein different combinations of decoded said bits are associated with different modes of address translation; an algorithmic function generator for providing a set of real-time translation functions including at least (a) logical block address to logical cylinder-head-sector address mode conversion, and (b) physical cylinder-head-sector address to physical block address mode conversion; a mode selector, coupled to said algorithmic function generator for selecting a chosen one from said set of translation functions in response to the decoded said bits; wherein said algorithmic function generator translates address space associated with said commands in response to the decoded said bits; said generator using an equation given by: X/Y=t0+r0 t0/Z=t1+r1 t1+W=r2 where X is said block address, Y is a physical sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone; means for testing whether the host CPU has written a command; a DONE register for testing whether said translator unit is presently available for translation; means for branching, in response to an output from said means for decoding, to a portion of said algorithmic function generator providing a real-time translation function corresponding to an output of said decoder; means for confirming that a host CPU command has been received, and if affirmative, means for reading task registers associated with said host CPU; wherein if said decoder determines that a multiplication function is required, said algorithmic function generator provides a multiplication function; wherein if said decoder determines that a division function is required, said algorithmic function generator provides a division function; wherein if said decoder determines that a said block address is to be converted to a cylinder-head-sector address said algorithmic function generator uses an equation given by: X/Y=t0+r0 t0/Z=t1+r1 t1+W=r2 where X is said block address, Y is a sector and track number, t0 is an integer quotient resulting from dividing X/Y, r0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a logical zone; wherein if said decoder determines that a said cylinder-head-sector address is to be converted to a block address, said translator unit confirms receipt of said host CPU command and reads said task registers associated with said host CPU, and converts said address using an equation given by: block address=((((C*Nh)+H)*Ns)+S-1) where C is a head number, Nh is a head and drive number, H is a head number, Ns is a sector and track number, and S is a sector number; and means for setting said DONE register means upon translation completion.

Claim 12

The method of claim 7 wherein said address spaces are associated with a hard disc controller unit buffer.

Claim 13

The method of claim 7, wherein the step of providing translates said address space using hardware selected from a group consisting of (a) a state machine, (b) a microcontroller, and (c) a local microprocessor associated with said translator unit.

Claim 14

The method of claim 7, wherein the step of providing further provides at least one additional function selected from a group consisting of (c) division, and (d) multiplication.

Claim 19

The method of claim 12, wherein a said address conversion is carried out using an equation given by: X/Y=t0+r0 t0/Z=t1+r1 t1+W=r2 where X is said block address, Y is a sector and track number, t0 is an integer quotient resulting from dividing X/Y, t0 is a remainder resulting from dividing X/Y, Z is a head and drive number, t1 is an integer quotient resulting from dividing t0/Z, r1 is a remainder resulting from dividing t0/Z, and W is a number denoting a starting cylinder for a zone.

Claim 20

The method of claim 12, wherein a said block address conversion is carried out using an equation given by; block address=((((C*Nh)+H)*Ns)+S-1) where C is a head number, Nh is a head and drive number, H is a head number, Ns is a sector and track number, and S is a sector number.