US5720006A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Expert system inference circuit
Assignee: Reticular Systems Inc
•
Filing: 1995-09-14
•
Granted: 1998-02-17
•
Expires: 2015-09-14
Abstract
Abstract A rule based processing system that is optimized for implementation in hardware. The system includes a set of logic gates that are used to implement a rule network connected to a working memory composed from a set of memory components. When a set of inputs are presented to the logic gates, a set of inferences are formed and the results are stored in the memory components. The inferences that are stored in the working memory are used to determine the state of the system at any given time. These inferences can be output to an external device to report on the status of the system. The rule based production system is designed to be implementable on a high performance semiconductor micro-chip and is thus suitable for use in embedded real-time applications.
Inventors
- 👤 Dan Ballard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:43
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06N; G06N5/00; G06N5/04; G06N5/046; G06N5/047; Y; Y10; Y10S; Y10S706/00; Y10S706/902; Y10S706/911; Y10S706/916
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
61 words
An inference circuit, comprising: a plurality of programmable function units representative of a rule network, each unit receiving a plurality of system condition signals and generating an action signal indicative of assertion or deassertion; and a working memory comprising a plurality of working memory elements wherein each element receives and stores the action signal for a selected one of the units.
Claim 2
Dependent Claim
61 words
An inference circuit, comprising: a plurality of programmable function units representative of a rule network, each unit receiving a plurality of system condition signals and generating an action signal indicative of assertion or deassertion; and a working memory comprising a plurality of working memory elements wherein each element receives and stores the action signal for a selected one of the units.
Claim 3
Dependent Claim
15 words
The inference circuit defined in claim 1, wherein each function unit comprises a static RAM.
Claim 4
Dependent Claim
14 words
The inference circuit defined in claim 2, wherein each memory element comprises a flip-flop.
Claim 5
Dependent Claim
31 words
The inference circuit defined in claim 1, wherein system condition signals or programmable signals are received by a tristate buffer in the programmable function unit and selectively fed to a RAM.
Claim 6
Dependent Claim
75 words
In an inference circuit having a plurality of programmable function units representative of a rule network and a working memory comprising a plurality of working memory elements, a method of inferencing, comprising the steps of: receiving a plurality of system condition signals at each programmable function unit; generating an action signal indicative of assertion or deassertion; and receiving and storing in a working memory element the action signal for a selected one of the units.
Claim 7
Dependent Claim
75 words
In an inference circuit having a plurality of programmable function units representative of a rule network and a working memory comprising a plurality of working memory elements, a method of inferencing, comprising the steps of: receiving a plurality of system condition signals at each programmable function unit; generating an action signal indicative of assertion or deassertion; and receiving and storing in a working memory element the action signal for a selected one of the units.
References Cited (Backward Citations)
US4649515A
Cited
US4837735A
Cited
EP0320957A2
Cited
US4922432A
Cited
US4939680A
Cited
US5218669A
Cited
US5063522A
Cited
US4924408A
Cited
US5072405A
Cited
CA1272291A
Cited
US5129037A
Cited
US5390286A
Cited
US5259066A
Cited
US5230061A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-16 | 2001-08-18 | 2002-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-16 | 2005-08-18 | 2006-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-16 | 2009-08-18 | 2010-02-17 | $7700.00 | Window Closed / Lapsed |