Method for manufacturing a semiconductor device having interconnection layers

Claim 1

A method for manufacturing a semiconductor device comprising the steps of: subsequent to sequentially forming first and second insulating films over a semiconductor substrate, forming a lower interconnection layer formation groove in the second and first insulating films by a lithography method and anisotropic etching technique; after forming a lower interconnection layer material on a whole surface of a resultant structure, removing the lower interconnection layer material by a chemical/mechanical polishing method on the second insulating film to leave the lower interconnection layer material as a buried lower interconnection layer in the lower interconnection layer formation groove; after sequentially forming first and second insulating interlayers on a whole surface of a resultant semiconductor structure, forming an upper interconnection layer formation groove by lithography technique and anisotropic etching technique in the second insulating interlayer; forming a via hole in the first insulating interlayer by the lithography technique and anisotropic etching technique at an area connecting an upper interconnection layer to the lower interconnection layer, the formation of the via hole being effected by the anisotropic etching technique at an etching rate over ten times the etching rates of the second insulating film and second insulating interlayer, and wherein the via hole has an opening diameter in a resist pattern corresponding to a sum of a width of the upper interconnection layer formation groove, an amount of misalignment at a resist patterning when forming the upper interconnection layer formation groove, and an amount of misalignment at a resist patterning when forming the via hole; and removing an upper interconnection layer material by the chemical/mechanical polishing method on the second insulating interlayer in a way to leave the upper interconnection layer material, as a buried upper interconnection layer, in the upper interconnection layer formation groove and via hole.

Claim 2

A method for manufacturing a semiconductor device comprising the steps of: subsequent to sequentially forming first and second insulating films over a semiconductor substrate, forming a lower interconnection layer formation groove in the second and first insulating films by a lithography method and anisotropic etching technique; after forming a lower interconnection layer material on a whole surface of a resultant structure, removing the lower interconnection layer material by a chemical/mechanical polishing method on the second insulating film to leave the lower interconnection layer material as a buried lower interconnection layer in the lower interconnection layer formation groove; after sequentially forming first and second insulating interlayers on a whole surface of a resultant semiconductor structure, forming an upper interconnection layer formation groove by lithography technique and anisotropic etching technique in the second insulating interlayer; forming a via hole in the first insulating interlayer by the lithography technique and anisotropic etching technique at an area connecting an upper interconnection layer to the lower interconnection layer, the formation of the via hole being effected by the anisotropic etching technique at an etching rate over ten times the etching rates of the second insulating film and second insulating interlayer, and wherein the via hole has an opening diameter in a resist pattern corresponding to a sum of a width of the upper interconnection layer formation groove, an amount of misalignment at a resist patterning when forming the upper interconnection layer formation groove, and an amount of misalignment at a resist patterning when forming the via hole; and removing an upper interconnection layer material by the chemical/mechanical polishing method on the second insulating interlayer in a way to leave the upper interconnection layer material, as a buried upper interconnection layer, in the upper interconnection layer formation groove and via hole.

Claim 3

A method for manufacturing a semiconductor device comprising the steps of: subsequent to sequentially forming first and second insulating films over a semiconductor substrate, forming a plurality of lower interconnection layer formation grooves in the second and first insulating films by a lithography method and anisotropic etching technique; after forming a lower interconnection layer material on a whole surface of a resultant structure, removing the lower interconnection layer material by a chemical/mechanical polishing method on the second insulating film to leave the lower interconnection layer material as a buried lower interconnection layer in the lower interconnection layer formation grooves; after sequentially forming first and second insulating interlayers on a whole surface of a resultant semiconductor structure, forming a plurality of upper interconnection layer formation grooves, by lithography technique and anisotropic etching technique, in the second insulating interlayer; forming a plurality of via holes in the first insulating interlayer by the lithography technique and anisotropic etching technique at an area connecting an upper interconnection layer to the lower interconnection layer, the formation of the via holes being effected by the anisotropic etching technique at an etching rate over ten times the etching rates of the second insulating film and second insulating interlayer, and wherein the plurality of via holes have an opening diameter in a resist pattern corresponding to a sum of widths of the upper interconnection layer formation grooves, amounts of misalignment at a resist patterning when forming the upper interconnection layer formation grooves, amounts of misalignment at a resist patterning when forming the via holes, and widths of the areas between adjacent upper interconnection layer formation grooves; and removing an upper interconnection layer material by the chemical/mechanical polishing method on the second insulating interlayer in a way to leave the upper interconnection layer material, as a buried upper interconnection layer, in the upper interconnection layer formation grooves and via holes.

Claim 4

A method for manufacturing a semiconductor device comprising the steps of: subsequent to sequentially forming first and second insulating films over a semiconductor substrate, forming a plurality of lower interconnection layer formation grooves in the second and first insulating films by a lithography method and anisotropic etching technique; after forming a lower interconnection layer material on a whole surface of a resultant structure, removing the lower interconnection layer material by a chemical/mechanical polishing method on the second insulating film to leave the lower interconnection layer material as a buried lower interconnection layer in the lower interconnection layer formation grooves; after sequentially forming first and second insulating interlayers on a whole surface of a resultant semiconductor structure, forming a plurality of upper interconnection layer formation grooves, by lithography technique and anisotropic etching technique, in the second insulating interlayer; forming a plurality of via holes in the first insulating interlayer by the lithography technique and anisotropic etching technique at an area connecting an upper interconnection layer to the lower interconnection layer, the formation of the via holes being effected by the anisotropic etching technique at an etching rate over ten times the etching rates of the second insulating film and second insulating interlayer, and wherein the plurality of via holes have an opening diameter in a resist pattern corresponding to a sum of widths of the upper interconnection layer formation grooves, amounts of misalignment at a resist patterning when forming the upper interconnection layer formation grooves, amounts of misalignment at a resist patterning when forming the via holes, and widths of the areas between adjacent upper interconnection layer formation grooves; and removing an upper interconnection layer material by the chemical/mechanical polishing method on the second insulating interlayer in a way to leave the upper interconnection layer material, as a buried upper interconnection layer, in the upper interconnection layer formation grooves and via holes.