← Back to Patent Explorer
US5721944A Expired / Lapsed US ⏱️ 0.0 years remaining

Method and system for implementing relative time discriminations in a high speed data transmission network

Assignee: Cisco Technology Inc
•
Filing: 1995-07-05
•
Granted: 1998-02-24
•
Expires: 2015-07-05
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A data transmission network congestion control mechanism requires knowledge of the sequence of occurrence of two dates d1 and d2, respectively defined by times t1 and t2 provided by a wraparound timer as respective numbers A and B coded in a 2's-complement form. Relative date discrimination is implemented by dividing the wraparound timer period into four consecutive intervals, each defined by the two most significant bits of the timer count. The value of the most significant bits and the sign of A-B, are used to derive a one-bit "X" indicator, the binary value of which indicates which of the two dates d1 and d2 was first to occur.

Inventors

  • 👤 Georges Gallet
  • 👤 Jean Marie Munier
  • 👤 Andre Pauporte
  • 👤 Victor Spagnol

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 22:25
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L12/5602; H04L2012/5629; H04L2012/5631; H04L2012/5636; H04L2012/5637

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 291 words
For use in a system including a timer, comprising a free running n-bit wraparound counter having a finite timer period, said timer counting from a maximum negative value having a predetermined absolute value to a maximum positive value having the same predetermined absolute value, and wherein the time of of an event is recorded as the current count in said timer when the event occurred, a method of determining which of two events occurring within a single timer period was the earlier, said method comprising the steps of: a) setting a first value A equal to the two most significant bits (MSBs) of a first timer count recorded when one of the two events occurred; b) setting a second value B equal to the two MSBs of a second timer count recorded when the other of the events occurred; c) setting a third value equal to binary 1 if the MSBs of A and B have the same binary value and if the MSB of the binary result of A minus B equals binary 1; d) setting a fourth value equal to binary 1 if the MSBs of A and B have different binary values and the second MSB of A equals binary 1; e) setting a fifth value equal to binary 1 if the MSBs of A an B have different binary values and the second MSB of B equals binary 0; f) If any of the third, fourth and fifth values equals binary 1, designating one of the first and second timer counts as being the first to occur; and g) if none of the third, fourth and fifith values equals binary 1, designating the other of the first and second timer counts as being the first to occur.
Claim 2
Dependent Claim 291 words
For use in a system including a timer, comprising a free running n-bit wraparound counter having a finite timer period, said timer counting from a maximum negative value having a predetermined absolute value to a maximum positive value having the same predetermined absolute value, and wherein the time of of an event is recorded as the current count in said timer when the event occurred, a method of determining which of two events occurring within a single timer period was the earlier, said method comprising the steps of: a) setting a first value A equal to the two most significant bits (MSBs) of a first timer count recorded when one of the two events occurred; b) setting a second value B equal to the two MSBs of a second timer count recorded when the other of the events occurred; c) setting a third value equal to binary 1 if the MSBs of A and B have the same binary value and if the MSB of the binary result of A minus B equals binary 1; d) setting a fourth value equal to binary 1 if the MSBs of A and B have different binary values and the second MSB of A equals binary 1; e) setting a fifth value equal to binary 1 if the MSBs of A an B have different binary values and the second MSB of B equals binary 0; f) If any of the third, fourth and fifth values equals binary 1, designating one of the first and second timer counts as being the first to occur; and g) if none of the third, fourth and fifith values equals binary 1, designating the other of the first and second timer counts as being the first to occur.
Claim 3
Dependent Claim 73 words
A method as set forth in claim 1 wherein the timer period is divided into four equal intervals beginning with interval in which the maximum negative value occurs, the two most significant bits of the first interval being 10, the two most significant bits of the second interval being 11, the two most significant bits of the third interval being 00 and the two most significant bits of the fourth interval being 01.

References Cited (Backward Citations)

US3971005A Cited
US4623846A Cited
US4905178A Cited
US5157655A Cited
JPH05252192A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-02-23 2001-08-25 2002-02-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-02-23 2005-08-25 2006-02-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-02-23 2009-08-25 2010-02-24 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag