US5732018A
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Self-contained reprogramming nonvolatile integrated circuit memory devices and methods
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-10-29
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Granted: 1998-03-24
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Expires: 2016-10-29
Abstract
Abstract Nonvolatile integrated circuit memory devices, such as EEPROMs, use unselected shared latching sense amplifiers to latch data from memory cells which are to be reprogrammed after a page erase, and to resupply the latch data to the memory cells which are to be programmed after erase, to thereby internally reprogram the latched data into erased memory cells after page programming. Transferring circuits and methods are provided for transferring data between shared latching sense amplifiers to permit internal reprogramming. High speed and simplified reprogramming of EEPROMs is thereby provided.
Inventors
- 👤 Do-chan Choi
- 👤 Tae-Sung Jung
- 👤 Woung-Moo Lee
- 👤 Ejaz Haq
- 👤 Syed Ali
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 00:51
CPC Classifications
G; G11; G11C; G11C16/00; G11C5/00; G11C5/02; G11C5/025; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C7/00; G11C7/10; G11C7/1051
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
257 words
A nonvolatile integrated circuit memory device comprising: a memory cell array, including a plurality of cell units arranged in rows and columns, each cell unit comprising a column of a plurality of serially connected memory cells, each of said memory cells comprising a floating gate and a control gate; a plurality of bit line pairs, each of which includes a first and a second bit line, one end of a respective cell unit being connected to a respective one of said bit lines in said plurality of bit line pairs; a plurality of word lines, a respective one of which is connected to the control gates of the memory cells of a plurality of cell units in a respective row; a plurality of shared latching sense amplifiers, a respective one of which is connected to the first and second bit lines of a respective bit line pair; and means for latching data from selected ones of said memory cells which are connected to a selected one of said word lines, into said plurality of shared latching sense amplifiers prior to erasing the memory cells which are connected to said selected one of said word lines, and for resupplying the latched data from said plurality of shared sense amplifiers to said selected ones of said memory cells which are connected to said selected one of said word lines after erasing the memory cells which are connected to said selected one of said word lines, to thereby internally reprogram the latched data into erased memory cells after page erasing.
Claim 2
Dependent Claim
257 words
A nonvolatile integrated circuit memory device comprising: a memory cell array, including a plurality of cell units arranged in rows and columns, each cell unit comprising a column of a plurality of serially connected memory cells, each of said memory cells comprising a floating gate and a control gate; a plurality of bit line pairs, each of which includes a first and a second bit line, one end of a respective cell unit being connected to a respective one of said bit lines in said plurality of bit line pairs; a plurality of word lines, a respective one of which is connected to the control gates of the memory cells of a plurality of cell units in a respective row; a plurality of shared latching sense amplifiers, a respective one of which is connected to the first and second bit lines of a respective bit line pair; and means for latching data from selected ones of said memory cells which are connected to a selected one of said word lines, into said plurality of shared latching sense amplifiers prior to erasing the memory cells which are connected to said selected one of said word lines, and for resupplying the latched data from said plurality of shared sense amplifiers to said selected ones of said memory cells which are connected to said selected one of said word lines after erasing the memory cells which are connected to said selected one of said word lines, to thereby internally reprogram the latched data into erased memory cells after page erasing.
Claim 3
Dependent Claim
99 words
A nonvolatile integrated circuit memory device according to claim 1 wherein said latching and resupplying means further comprises: means for transferring latched data from selected ones of said plurality of shared sense amplifiers to selected others of said plurality of shared sense amplifiers prior to erasing the memory cells which are connected to said selected one of said word lines, and for retransferring latched data from said selected others of said shared sense amplifiers to said selected ones of said shared sense amplifiers after erasing the memory cells which are connected to said selected one of said word lines.
Claim 4
Dependent Claim
94 words
A nonvolatile integrated circuit memory device according to claim 1 wherein said latching and resupplying means further comprises: a plurality of data inverting circuits, a respective one of which is connected between a respective bit line pair and a respective shared latching sense amplifier, to invert the data from selected ones of said memory cells which are connected to a selected one of said word lines which is latched into said plurality of shared latching sense amplifiers prior to erasing the memory cells which are connected to said selected one of said word lines.
Claim 5
Dependent Claim
71 words
A nonvolatile integrated circuit memory device according to claim 3 further comprising: means for disabling said plurality of data inverting circuits from inverting the latched data which is resupplied from said plurality of shared sense amplifiers to said selected ones of said memory cells which are connected to said selected one of said word lines after erasing the memory cells which are connected to said selected one of said word lines.
Claim 6
Dependent Claim
76 words
A nonvolatile integrated circuit memory device according to claim 1 further comprising: means for supplying a program inhibit voltage to unselected ones of said first and second bit lines when resupplying the latched data from said plurality of shared sense amplifiers to said selected ones of said memory cells which are connected to said selected one of said word lines after erasing the memory cells which are connected to said selected one of said word lines.
Claim 7
Dependent Claim
214 words
A nonvolatile integrated circuit memory device comprising: a memory cell array including at least first and second subarrays, each subarray including a plurality of cell units arranged in rows and columns, each cell unit comprising a column of a plurality of serially connected memory cells, each of said memory cells comprising a floating gate and a control gate; each subarray further including a plurality of bit line pairs, each of which includes a first and a second bit line, one end of a respective cell unit being connected to a respective one of said bit lines in said plurality of bit line pairs, and a plurality of word lines, a respective one of which is connected to the control gate of the memory cells of a plurality of cell units in a respective row; each subarray further including a plurality of shared latching sense amplifiers, a respective one of which is connected to the first and second bit lines of a respective bit line pair; and data transferring means, connected to the shared latching sense amplifiers in said first subarray and said second subarray, for transferring sensed and latched data between said plurality of shared latching sense amplifiers in said first subarray and said plurality of shared latching sense amplifiers in said second subarray.
Claim 8
Dependent Claim
214 words
A nonvolatile integrated circuit memory device comprising: a memory cell array including at least first and second subarrays, each subarray including a plurality of cell units arranged in rows and columns, each cell unit comprising a column of a plurality of serially connected memory cells, each of said memory cells comprising a floating gate and a control gate; each subarray further including a plurality of bit line pairs, each of which includes a first and a second bit line, one end of a respective cell unit being connected to a respective one of said bit lines in said plurality of bit line pairs, and a plurality of word lines, a respective one of which is connected to the control gate of the memory cells of a plurality of cell units in a respective row; each subarray further including a plurality of shared latching sense amplifiers, a respective one of which is connected to the first and second bit lines of a respective bit line pair; and data transferring means, connected to the shared latching sense amplifiers in said first subarray and said second subarray, for transferring sensed and latched data between said plurality of shared latching sense amplifiers in said first subarray and said plurality of shared latching sense amplifiers in said second subarray.
Claim 9
Dependent Claim
183 words
A nonvolatile integrated circuit memory device according to claim 6 wherein said data transferring means comprises: means for latching data from selected ones of said memory cells which are connected to a selected one of said word lines in a selected one of said first and second subarrays into said plurality of shared latching sense amplifiers in said unselected one of said first and second subarrays prior to erasing the memory cells which are connected to said selected one of said word lines in said selected one of said first and second subarrays, and for resupplying the latched data from said plurality of shared sense amplifiers in said unselected one of said first and second subarrays to said selected ones of said memory cells which are connected to said selected one of said word lines in said selected one of said first and second subarrays after erasing the memory cells which are connected to said selected one of said word lines in said selected one of said first and second subarrays, to thereby internally reprogram data into erased memory cells after page erasing.
Claim 10
Dependent Claim
161 words
A nonvolatile integrated circuit memory device according to claim 6 wherein said data transferring means comprises: means for latching data which is stored at unselected memory cells which do not require reprogramming and which are connected to a selected word line of a selected one of said first and second memory subarrays; into said plurality of shared latching sense amplifiers in said selected one of said first and second memory subarrays via the unselected bit lines of said first and second bit lines which are associated with said unselected memory cells prior to erasing the memory cells which are connected to said selected one of said word lines in said selected one of said first and second subarrays, and for transferring the data latched into said plurality of shared latching sense amplifiers in said selected one of said first and second memory subarrays to said plurality of shared latching sense amplifiers in the other of said first and second memory subarrays.
Claim 11
Independent Claim
251 words
A method of reprogramming a nonvolatile integrated circuit memory device having a memory cell array, including a plurality of cell units arranged in rows and columns, each cell unit comprising a column of a plurality of serially connected memory cells, each of said memory cells comprising a floating gate and a control gate; a plurality of bit line pairs, each of which includes a first and a second bit line, one end of a respective cell unit being connected to a respective one of said bit lines in said plurality of bit line pairs; a plurality of word lines, a respective one of which is connected to the control gate of the memory cells of a plurality of cell units in a respective row; and a plurality of shared latching sense amplifiers, a respective one of which is connected to the first and second bit lines of a respective bit line pair; said reprogramming method comprising the steps of: latching data from selected ones of said memory cells which are connected to a selected one of said word lines into said plurality of shared latching sense amplifiers prior to erasing the memory cells which are connected to said selected one of said word lines; and resupplying the latched data from said plurality of shared sense amplifiers to said selected ones of said memory cells which are connected to said selected one of said word lines, after erasing the memory cells which are connected to said selected one of said word lines.
Claim 12
Independent Claim
251 words
A method of reprogramming a nonvolatile integrated circuit memory device having a memory cell array, including a plurality of cell units arranged in rows and columns, each cell unit comprising a column of a plurality of serially connected memory cells, each of said memory cells comprising a floating gate and a control gate; a plurality of bit line pairs, each of which includes a first and a second bit line, one end of a respective cell unit being connected to a respective one of said bit lines in said plurality of bit line pairs; a plurality of word lines, a respective one of which is connected to the control gate of the memory cells of a plurality of cell units in a respective row; and a plurality of shared latching sense amplifiers, a respective one of which is connected to the first and second bit lines of a respective bit line pair; said reprogramming method comprising the steps of: latching data from selected ones of said memory cells which are connected to a selected one of said word lines into said plurality of shared latching sense amplifiers prior to erasing the memory cells which are connected to said selected one of said word lines; and resupplying the latched data from said plurality of shared sense amplifiers to said selected ones of said memory cells which are connected to said selected one of said word lines, after erasing the memory cells which are connected to said selected one of said word lines.
Claim 13
Dependent Claim
98 words
A method according to claim 9: wherein said latching step comprises the step of transferring data from selected ones of said plurality of shared sense amplifiers to selected others of said plurality of shared sense amplifiers prior to erasing the memory cells which are connected to said selected one of said word lines; and wherein said resupplying step comprises the step of retransferring data from said selected others of said shared sense amplifiers to said selected ones of said shared sense amplifiers after erasing the memory cells which are connected to said selected one of said word lines.
Claim 14
Independent Claim
120 words
A method of reprogramming a nonvolatile integrated circuit memory device comprising a memory cell array including at least first and second subarrays, each subarray including a plurality of nonvolatile memory cells arranged in rows and columns, a plurality of bit line pairs, each of which includes a first and a second bit line, and a plurality of shared latching sense amplifiers, a respective one of which is connected to the first and second bit lines of a respective bit line pair; said reprogramming method comprising the step of: using shared latching sense amplifiers in said second subarray, to latch data from memory cells in said first subarray, which are to be reprogrammed after a page erase of said first subarray.
Claim 15
Independent Claim
120 words
A method of reprogramming a nonvolatile integrated circuit memory device comprising a memory cell array including at least first and second subarrays, each subarray including a plurality of nonvolatile memory cells arranged in rows and columns, a plurality of bit line pairs, each of which includes a first and a second bit line, and a plurality of shared latching sense amplifiers, a respective one of which is connected to the first and second bit lines of a respective bit line pair; said reprogramming method comprising the step of: using shared latching sense amplifiers in said second subarray, to latch data from memory cells in said first subarray, which are to be reprogrammed after a page erase of said first subarray.
Claim 16
Dependent Claim
43 words
A method according to claim 11 wherein said using step comprises the step of: transferring sensed and latched data between said plurality of shared latching sense amplifiers in said first subarray and said plurality of shared latching sense amplifiers in said second subarray.
Claim 17
Dependent Claim
192 words
A method according to claim 12 wherein said memory device further includes a plurality of word lines, a respective one of which is connected to the memory cells in a respective row, and said transferring step comprises the steps of: latching data from selected ones of said memory cells which are connected to a selected one of said word lines in a selected one of said first and second subarrays into said plurality of shared latching sense amplifiers in said unselected one of said first and second subarrays prior to erasing the memory cells which are connected to said selected one of said word lines in said selected one of said first and second subarrays; and resupplying the latched data from said plurality of shared sense amplifiers in said unselected one of said first and second subarrays to said selected ones of said memory cells which are connected to said selected one of said word lines in said selected one of said first and second subarrays after erasing the memory cells which are connected to said selected one of said word lines in said selected one of said first and second subarrays.
Claim 18
Dependent Claim
182 words
A method according to claim 12 wherein said memory device further includes a plurality of word lines, a respective one of which is connected to the memory cells in a respective row, and said transferring step comprises the steps of: latching data which is stored at unselected memory cells which do not require reprogramming and which are connected to a selected word line of a selected one of said first and second memory subarrays; into said plurality of shared latching sense amplifiers in said selected one of said first and second memory subarrays via the unselected bit lines of said first and second bit lines which are associated with said unselected memory cells prior to erasing the memory cells which are connected to said selected one of said word lines in said selected one of said first and second subarrays; and transferring the data latched into said plurality of shared latching sense amplifiers in said selected one of said first and second memory subarrays to said plurality of shared latching sense amplifiers in the other of said first and second memory subarrays.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-23 | 2001-09-22 | 2002-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-23 | 2005-09-22 | 2006-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-23 | 2009-09-22 | 2010-03-24 | $7700.00 | Window Closed / Lapsed |