Method for manufacturing DRAM device using high dielectric constant

Claim 1

A method of manufacturing a capacitor structure of a semiconductor device, the method comprising the steps of: forming a gate electrode and a gate sidewall on a semiconductor substrate in which a field oxide film is formed on a device isolating region; forming impurity diffusion regions having an LDD structure in the semiconductor substrate on different sides of the gate electrode; forming first, second, third, and fourth insulating layers over the semiconductor substrate, coating and patterning a photoresist over the insulating layers, and sequentially etching the fourth insulating layer, the third insulating layer, and the second insulating layer to thereby form a contact hole in the fourth, third, and second insulating layers; forming a first electrode material layer over the semiconductor substrate and anisotropically etching the first electrode material layer so as leave only a portion of the first electrode material on a wall of the contact hole, the portion of the first electrode material on the wall of the contact hole forming a first conductive sidewall; removing a portion of the first insulating layer located below the contact hole by using the first conductive sidewall as a mask, and forming a second electrode material layer over the semiconductor substrate, a plurality of the insulating layers, and the first conductive sidewall; forming a planarizing layer over a surface of the semiconductor substrate over which the second electrode material layer is formed, and etching back the planarizing layer until the second electrode material layer is exposed; removing an exposed portion of the second electrode material layer and at least a portion of the third insulating layer, and forming a third electrode material layer to a predetermined thickness over the semiconductor substrate; anisotropically etching the third electrode material layer to thereby form a second conductive sidewall on a side of the first conductive sidewall; removing a portion of the planarizing layer remaining in the contact hole and forming a dielectric layer over the semiconductor substrate; and forming an upper electrode of a capacitor on the dielectric layer.

Claim 2

A method of manufacturing a capacitor structure of a semiconductor device, the method comprising the steps of: forming a gate electrode and a gate sidewall on a semiconductor substrate in which a field oxide film is formed on a device isolating region; forming impurity diffusion regions having an LDD structure in the semiconductor substrate on different sides of the gate electrode; forming first, second, third, and fourth insulating layers over the semiconductor substrate, coating and patterning a photoresist over the insulating layers, and sequentially etching the fourth insulating layer, the third insulating layer, and the second insulating layer to thereby form a contact hole in the fourth, third, and second insulating layers; forming a first electrode material layer over the semiconductor substrate and anisotropically etching the first electrode material layer so as leave only a portion of the first electrode material on a wall of the contact hole, the portion of the first electrode material on the wall of the contact hole forming a first conductive sidewall; removing a portion of the first insulating layer located below the contact hole by using the first conductive sidewall as a mask, and forming a second electrode material layer over the semiconductor substrate, a plurality of the insulating layers, and the first conductive sidewall; forming a planarizing layer over a surface of the semiconductor substrate over which the second electrode material layer is formed, and etching back the planarizing layer until the second electrode material layer is exposed; removing an exposed portion of the second electrode material layer and at least a portion of the third insulating layer, and forming a third electrode material layer to a predetermined thickness over the semiconductor substrate; anisotropically etching the third electrode material layer to thereby form a second conductive sidewall on a side of the first conductive sidewall; removing a portion of the planarizing layer remaining in the contact hole and forming a dielectric layer over the semiconductor substrate; and forming an upper electrode of a capacitor on the dielectric layer.