Integrated memory circuit with sequenced bitlines for stress test

Claim 1

An integrated circuit comprising: a memory array having a plurality of memory cells arranged in rows and columns; a column decoder having column terminals and bidirectional read/write terminals; a boundary area located between said memory array and said column decoder such that none of the memory cells that are located within said memory array are located on the same side of said boundary area as said column decoder, wherein each column includes a plurality of memory cells connected in parallel by way of a pair of true and complement bitlines that extend out from the memory array and that are coupled to the column terminals of the column decoder, at least one pair of said bitlines crossing over one another within said boundary area; and wherein, inside the memory array, the true bitline of each pair is adjacent exclusively to a complement bitline of another pair of true and complement bitlines and the complement bitline of said each pair is adjacent exclusively to a true bitline of another pair of true and complement bitlines, the true and complement bit lines being so exclusively adjacent to one another along the entire lengths of the respective bitline portions that are inside the memory array.

Claim 18

A method for stress testing an integrated memory circuit including a memory array having a plurality of memory cells arranged in rows and columns, a first logic circuitry including column decoder circuitry, a boundary region that extends between the memory array and the column decoder circuitry such that no portion of the memory array is located on a side of the boundary region where the column decoder circuitry is located, and a second logic circuitry coupled to the memory array and including row decoder circuitry, wherein each column includes a plurality of memory cells connected in parallel by way of a pair of true and complement bitlines that couple the memory array to the first logic circuitry, wherein, inside the memory array, the true bitline of each pair is adjacent exclusively to a complement bitline of another pair of true and complement bitlines along the full length of the true-bitline section that is within the array, and the complement bitline of said each pair is adjacent exclusively to a true bitline of another pair of true and complement bitlines along the full length of the complement-bitline section that is within the array, and wherein outside the memory array and within the boundary region one or more pairs of said bitlines are twisted, the method comprising the steps of: simultaneously setting a plurality of inputs of the column decoder circuitry to a first common voltage level and a plurality of inputs of the row decoder circuitry to a second common voltage level; and applying a stress voltage to the memory array for a predetermined time period to stress isolation regions that are located between adjacent bitlines.

Claim 19

A method for stress testing an integrated memory circuit including a memory array having a plurality of memory cells arranged in rows and columns, a first logic circuitry including column decoder circuitry, a boundary region that extends between the memory array and the column decoder circuitry such that no portion of the memory array is located on a side of the boundary region where the column decoder circuitry is located, and a second logic circuitry coupled to the memory array and including row decoder circuitry, wherein each column includes a plurality of memory cells connected in parallel by way of a pair of true and complement bitlines that couple the memory array to the first logic circuitry, wherein, inside the memory array, the true bitline of each pair is adjacent exclusively to a complement bitline of another pair of true and complement bitlines along the full length of the true-bitline section that is within the array, and the complement bitline of said each pair is adjacent exclusively to a true bitline of another pair of true and complement bitlines along the full length of the complement-bitline section that is within the array, and wherein outside the memory array and within the boundary region one or more pairs of said bitlines are twisted, the method comprising the steps of: simultaneously setting a plurality of inputs of the column decoder circuitry to a first common voltage level and a plurality of inputs of the row decoder circuitry to a second common voltage level; and applying a stress voltage to the memory array for a predetermined time period to stress isolation regions that are located between adjacent bitlines.