US5751665A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock distributing circuit
Assignee: Lapis Semiconductor Co Ltd
•
Filing: 1996-07-21
•
Granted: 1998-05-12
•
Expires: 2016-07-21
Abstract
Abstract A clock distributing circuit, that comprises a clock distribution output circuit for inputting an external clock, outputting a first clock that synchronizes with the external clock, and distributing the first clock to each of load circuits, and a distributed clock input circuit disposed on input stages of all or part of the load circuits and adapted for inputting the first clock and outputting a second clock that synchronizes with the input clock, wherein one of the clock distribution output circuit and the distributed clock input circuit includes a phase difference-voltage converting circuit for converting the phase difference between the input clock and the output clock into a voltage, and a voltage control type delay circuit for delaying the input clock corresponding to an output voltage of the phase difference-voltage converting circuit and for outputting the delayed input clock.
Inventors
- 👤 Satoru Tanoi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:42
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
169 words
A clock distributing circuit, comprising: a clock distribution output circuit having a voltage control type delay circuit and a phase difference-voltage converting circuit, wherein the voltage control type delay circuit is for delaying a first clock in response to a first control voltage and for outputting a second clock obtained by delaying the first clock, and wherein the phase difference-voltage converting circuit is for converting a phase difference between the first clock and the second clock into the first control voltage; and a plurality of distributed clock input circuits coupled to the voltage control type delay circuit, each of the distributed clock input circuits having a voltage control type oscillator and a phase/frequency difference-voltage converting circuit, wherein the voltage control type oscillator is for varying a frequency and a phase of a third clock output therefrom in response to a second control voltage, and wherein the phase/frequency difference-voltage converting circuit is for converting a phase/frequency difference between the second clock and the third clock into the second control voltage.
Claim 2
Dependent Claim
169 words
A clock distributing circuit, comprising: a clock distribution output circuit having a voltage control type delay circuit and a phase difference-voltage converting circuit, wherein the voltage control type delay circuit is for delaying a first clock in response to a first control voltage and for outputting a second clock obtained by delaying the first clock, and wherein the phase difference-voltage converting circuit is for converting a phase difference between the first clock and the second clock into the first control voltage; and a plurality of distributed clock input circuits coupled to the voltage control type delay circuit, each of the distributed clock input circuits having a voltage control type oscillator and a phase/frequency difference-voltage converting circuit, wherein the voltage control type oscillator is for varying a frequency and a phase of a third clock output therefrom in response to a second control voltage, and wherein the phase/frequency difference-voltage converting circuit is for converting a phase/frequency difference between the second clock and the third clock into the second control voltage.
Claim 3
Dependent Claim
167 words
A clock distributing circuit, comprising: a clock distribution output circuit having a voltage control type oscillator and a phase/frequency difference-voltage converting circuit, wherein the phase/frequency difference-voltage converting circuit is for converting a phase/frequency difference between a first clock and a second clock into a first control voltage, and wherein the voltage control type oscillator is for varying a frequency and a phase of the second clock output therefrom in response to the first control voltage; a plurality of distributed clock input circuits coupled to the voltage control type oscillator, each of the distributed clock input circuits having a voltage control type delay circuit and a phase difference-voltage converting circuit, wherein the voltage control type delay circuit is for delaying the second clock in response to a second control voltage and for outputting a third clock obtained by delaying the second clock, and wherein the phase difference-voltage converting circuit is for converting a phase difference between the second clock and the third clock into the second control voltage.
Claim 4
Dependent Claim
167 words
A clock distributing circuit, comprising: a clock distribution output circuit having a voltage control type oscillator and a phase/frequency difference-voltage converting circuit, wherein the phase/frequency difference-voltage converting circuit is for converting a phase/frequency difference between a first clock and a second clock into a first control voltage, and wherein the voltage control type oscillator is for varying a frequency and a phase of the second clock output therefrom in response to the first control voltage; a plurality of distributed clock input circuits coupled to the voltage control type oscillator, each of the distributed clock input circuits having a voltage control type delay circuit and a phase difference-voltage converting circuit, wherein the voltage control type delay circuit is for delaying the second clock in response to a second control voltage and for outputting a third clock obtained by delaying the second clock, and wherein the phase difference-voltage converting circuit is for converting a phase difference between the second clock and the third clock into the second control voltage.
Claim 5
Dependent Claim
226 words
A clock distributing circuit, comprising: a clock distribution output circuit having a voltage control type oscillator, a voltage control type delay circuit and a phase/frequency difference-voltage converting circuit, wherein the voltage control type oscillator is for varying a frequency and a phase of a clock output therefrom in response to a first control voltage, wherein the voltage control type delay circuit is for delaying a first clock in response to a second control voltage and for outputting a second clock and a third clock, the second clock having a phase with an advance relative to a phase of the first clock, the third clock having a phase with a delay relative to the phase of the first clock, and wherein the phase/frequency difference-voltage converting circuit is for converting a phase/frequency difference between the first clock and the clock output from the voltage control type oscillator into the first control voltage and the second control voltage; and a plurality of distributed clock input circuits coupled to the voltage control type delay circuit, each of the distributed clock input circuits having a phase difference-voltage converting circuit for converting a phase difference between the first clock and a fourth clock into a third control voltage, the voltage control type phase shifter for generating the fourth clock in response to the second and third clock, and the third control voltage.
Claim 6
Dependent Claim
226 words
A clock distributing circuit, comprising: a clock distribution output circuit having a voltage control type oscillator, a voltage control type delay circuit and a phase/frequency difference-voltage converting circuit, wherein the voltage control type oscillator is for varying a frequency and a phase of a clock output therefrom in response to a first control voltage, wherein the voltage control type delay circuit is for delaying a first clock in response to a second control voltage and for outputting a second clock and a third clock, the second clock having a phase with an advance relative to a phase of the first clock, the third clock having a phase with a delay relative to the phase of the first clock, and wherein the phase/frequency difference-voltage converting circuit is for converting a phase/frequency difference between the first clock and the clock output from the voltage control type oscillator into the first control voltage and the second control voltage; and a plurality of distributed clock input circuits coupled to the voltage control type delay circuit, each of the distributed clock input circuits having a phase difference-voltage converting circuit for converting a phase difference between the first clock and a fourth clock into a third control voltage, the voltage control type phase shifter for generating the fourth clock in response to the second and third clock, and the third control voltage.
Claim 7
Dependent Claim
186 words
A clock distributing circuit comprising: a first clock synchronizing circuit having a first voltage control type oscillator and a first phase/frequency difference-voltage converting circuit, wherein the first voltage control type oscillator is for varying a frequency and a phase of a clock output therefrom in response to a reference voltage and a first control voltage, and wherein the first phase/frequency difference-voltage converting circuit is for converting a first phase/frequency difference between a first clock and the clock output from the first voltage control type oscillator into the first control voltage and a second control voltage; and a second clock synchronizing circuit having a second voltage control type oscillator and a second phase/frequency difference-voltage converting circuit, wherein the second voltage control type oscillator is for varying a frequency and a phase of a clock output therefrom in response to the second control voltage and a third control voltage, and wherein the second phase/frequency difference-voltage converting circuit is for converting a phase/frequency difference between the first clock and the clock output from the second voltage control type oscillator into the third control voltage and a fourth control voltage.
Claim 8
Dependent Claim
186 words
A clock distributing circuit comprising: a first clock synchronizing circuit having a first voltage control type oscillator and a first phase/frequency difference-voltage converting circuit, wherein the first voltage control type oscillator is for varying a frequency and a phase of a clock output therefrom in response to a reference voltage and a first control voltage, and wherein the first phase/frequency difference-voltage converting circuit is for converting a first phase/frequency difference between a first clock and the clock output from the first voltage control type oscillator into the first control voltage and a second control voltage; and a second clock synchronizing circuit having a second voltage control type oscillator and a second phase/frequency difference-voltage converting circuit, wherein the second voltage control type oscillator is for varying a frequency and a phase of a clock output therefrom in response to the second control voltage and a third control voltage, and wherein the second phase/frequency difference-voltage converting circuit is for converting a phase/frequency difference between the first clock and the clock output from the second voltage control type oscillator into the third control voltage and a fourth control voltage.
Claim 9
Dependent Claim
180 words
A clock distributing circuit comprising: a first clock synchronizing circuit having a first voltage control type delay circuit and a first phase difference-voltage converting circuit, wherein the first voltage control type delay circuit is for delaying a first clock in response to a reference voltage and a first control voltage and for outputting a second clock obtained by delaying the first clock, and wherein the first phase difference-voltage converting circuit is for converting a phase difference between the first clock and the second clock into the first control voltage and a second control voltage; and a second clock synchronizing circuit having a second voltage control type delay circuit and a second phase difference-voltage converting circuit, wherein the second voltage control type delay circuit is for delaying a first clock in response to the second control voltage and a third control voltage and for outputting a third clock obtained by delaying the first clock, and wherein the second phase difference-voltage converting circuit is for converting a phase difference between the first clock and the third clock into the third control voltage.
Claim 10
Dependent Claim
180 words
A clock distributing circuit comprising: a first clock synchronizing circuit having a first voltage control type delay circuit and a first phase difference-voltage converting circuit, wherein the first voltage control type delay circuit is for delaying a first clock in response to a reference voltage and a first control voltage and for outputting a second clock obtained by delaying the first clock, and wherein the first phase difference-voltage converting circuit is for converting a phase difference between the first clock and the second clock into the first control voltage and a second control voltage; and a second clock synchronizing circuit having a second voltage control type delay circuit and a second phase difference-voltage converting circuit, wherein the second voltage control type delay circuit is for delaying a first clock in response to the second control voltage and a third control voltage and for outputting a third clock obtained by delaying the first clock, and wherein the second phase difference-voltage converting circuit is for converting a phase difference between the first clock and the third clock into the third control voltage.
Claim 11
Dependent Claim
208 words
A clock distributing circuit comprising: a first clock synchronizing circuit having a first voltage control type oscillator and a first phase/frequency difference-voltage converting circuit, wherein the first voltage control type oscillator is for varying a frequency and a phase of a clock output therefrom in response to a reference voltage and a first control voltage, and wherein the first phase/frequency difference-voltage converting circuit is for converting a phase/frequency difference between the first clock and the clock output from the first voltage control type oscillator into the first control voltage and a second control voltage; and a plurality of second clock synchronizing circuits coupled to the first clock synchronizing circuit, each of the second clock synchronizing circuits having a second voltage control type oscillator and a second phase/frequency difference-voltage converting circuit, wherein the second voltage control type oscillator is for varying a frequency and a phase of a clock output therefrom in response to the second control voltage and a third control voltage, and wherein the second phase/frequency difference-voltage converting circuit is for converting a phase/frequency difference between the clock output from the first voltage control type oscillator and the clock output from the second voltage control type oscillator into the third control voltage and a fourth control voltage.
Claim 12
Dependent Claim
208 words
A clock distributing circuit comprising: a first clock synchronizing circuit having a first voltage control type oscillator and a first phase/frequency difference-voltage converting circuit, wherein the first voltage control type oscillator is for varying a frequency and a phase of a clock output therefrom in response to a reference voltage and a first control voltage, and wherein the first phase/frequency difference-voltage converting circuit is for converting a phase/frequency difference between the first clock and the clock output from the first voltage control type oscillator into the first control voltage and a second control voltage; and a plurality of second clock synchronizing circuits coupled to the first clock synchronizing circuit, each of the second clock synchronizing circuits having a second voltage control type oscillator and a second phase/frequency difference-voltage converting circuit, wherein the second voltage control type oscillator is for varying a frequency and a phase of a clock output therefrom in response to the second control voltage and a third control voltage, and wherein the second phase/frequency difference-voltage converting circuit is for converting a phase/frequency difference between the clock output from the first voltage control type oscillator and the clock output from the second voltage control type oscillator into the third control voltage and a fourth control voltage.
Claim 13
Dependent Claim
195 words
A clock distributing circuit comprising: a first clock synchronizing circuit having a first voltage control type delay circuit and a first phase difference-voltage converting circuit, wherein the first voltage control type delay circuit is for delaying a first clock in response to a reference voltage and a first control voltage and for outputting a second clock obtained by delaying the first clock, and wherein the first phase difference-voltage converting circuit is for converting a phase difference between the first clock and the second clock into the first control voltage and a second control voltage; and a plurality of second clock synchronizing circuits coupled to the first clock synchronizing circuit, each of the second clock synchronizing circuits having a second voltage control type delay circuit and a second phase difference-voltage converting circuit, wherein the second voltage control type delay circuit is for delaying a second clock in response to a third control voltage and second control voltage and for outputting a third clock obtained by delaying the second clock, and wherein the second phase difference-voltage converting circuit is for converting a phase difference between the second clock and the third clock into the third control voltage.
Claim 14
Dependent Claim
195 words
A clock distributing circuit comprising: a first clock synchronizing circuit having a first voltage control type delay circuit and a first phase difference-voltage converting circuit, wherein the first voltage control type delay circuit is for delaying a first clock in response to a reference voltage and a first control voltage and for outputting a second clock obtained by delaying the first clock, and wherein the first phase difference-voltage converting circuit is for converting a phase difference between the first clock and the second clock into the first control voltage and a second control voltage; and a plurality of second clock synchronizing circuits coupled to the first clock synchronizing circuit, each of the second clock synchronizing circuits having a second voltage control type delay circuit and a second phase difference-voltage converting circuit, wherein the second voltage control type delay circuit is for delaying a second clock in response to a third control voltage and second control voltage and for outputting a third clock obtained by delaying the second clock, and wherein the second phase difference-voltage converting circuit is for converting a phase difference between the second clock and the third clock into the third control voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-11 | 2001-11-10 | 2002-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-11 | 2005-11-10 | 2006-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-11 | 2009-11-10 | 2010-05-12 | $7700.00 | Window Closed / Lapsed |