Horizontal deflection circuit for multiscan type display devices

Claim 2

A multiscan compatible horizontal deflection driving circuit for supplying a driving power source voltage and a horizontal driving pulse to a horizontal deflecting circuit of a CRT, comprising: first control voltage generating means for generating a first control voltage of a magnitude corresponding to a frequency of a horizontal synchronization pulse, said first control voltage determining a voltage level of said driving power source voltage; driving power source voltage generating means for generating the driving power source voltage according to said first control voltage; second control voltage generating means for generating a second control voltage of a magnitude corresponding to the frequency of said horizontal synchronization pulse, said second control voltage determining a frequency of said horizontal driving pulse; and horizontal driving pulse generating means for generating the horizontal driving pulse of a frequency according to said second control voltage; wherein the first control voltage from said first control voltage generating means is generated earlier than the second control voltage from said second control voltage generating means when the frequency of the horizontal synchronization pulse decreases.

Claim 3

A multiscan compatible horizontal deflection driving circuit for supplying a driving power source voltage and a horizontal driving pulse to a horizontal deflecting circuit of a CRT, comprising: frequency voltage converting means for generating a frequency voltage of a magnitude corresponding to a frequency of a horizontal synchronization pulse; means for generating a voltage pulse which corresponds to said frequency voltage and having a phase which is synchronized with that of said horizontal synchronization pulse; first smoothing means for smoothing said voltage pulse, thereby forming a DC voltage; first delay means for delaying the DC voltage smoothed by said first smoothing means, thereby forming a first delay voltage; a converter power source for forming a voltage according to a level of said first delay voltage as a driving power source voltage; second smoothing means for smoothing said voltage pulse, thereby forming a DC voltage; second delay means for delaying the DC voltage smoothed by said second smoothing means, thereby forming a second delay voltage; and horizontal driving pulse forming means for forming the horizontal driving pulse which corresponds to said second delay voltage and having a phase which is synchronized with that of said voltage pulse; wherein said first delay means has a delay time which is shorter than a delay time of said second delay means when a level of an input DC voltage decreases.

Claim 4

A multiscan compatible horizontal deflection driving circuit for supplying a driving power source voltage and a horizontal driving pulse to a horizontal deflecting circuit of a CRT, comprising: frequency voltage converting means for generating a frequency voltage of a magnitude corresponding to a frequency of a horizontal synchronization pulse; means for generating a voltage pulse which corresponds to said frequency voltage and having a phase which is synchronized with that of said horizontal synchronization pulse; first smoothing means for smoothing said voltage pulse, thereby forming a DC voltage; first delay means for delaying the DC voltage smoothed by said first smoothing means, thereby forming a first delay voltage; a converter power source for forming a voltage according to a level of said first delay voltage as a driving power source voltage; second smoothing means for smoothing said voltage pulse, thereby forming a DC voltage; second delay means for delaying the DC voltage smoothed by said second smoothing means, thereby forming a second delay voltage; and horizontal driving pulse forming means for forming the horizontal driving pulse which corresponds to said second delay voltage and having a phase which is synchronized with that of said voltage pulse; wherein said first delay means has a delay time which is shorter than a delay time of said second delay means when a level of an input DC voltage decreases.

Claim 5

A circuit according to claim 2, wherein when the level of the input DC voltage decreases, said first delay means has a delay time which is shorter than its delay time when the level of the input DC voltage increases, and when the level of the input DC voltage decreases, said second delay means has a delay time which is longer than its delay time when the level of the input DC voltage increases.