Timing and control circuit and method for a synchronous vector processor

Claim 2

A timing controller for generating output signals including control and timing signals for a video or image processing device responsive to input signals including clock, horizontal synchronization, and vertical synchronization signals extracted from incoming video signals, said timing controller comprising: a master controller; and at least two timing generators said master controller generating first signals responsive to said input signals, providing said first signals to a first of said timing generators, and, together with said first generator, providing second signals to a second of said timing generators; said first generator generating third signals responsive to said first signals; said third signals including a part of said second signals; said second generator providing fourth signals responsive to said second signals; said fourth signals including a portion of said output signals and being synchronized with said horizontal and vertical synchronization signals.

Claim 3

The timing controller of claim 1, said second generator comprising: a constant generator; said fourth signals comprising operating constants.

Claim 4

The timing controller of claim 1, said master controller further comprising: auxiliary control means for selectively controlling writing placement of operating variables for said video or image processing device in an auxiliary register set.

Claim 5

The timing controller of claim 1, said master controller comprising: means for enabling subroutine jump and call operations.

Claim 6

The timing controller of claim 1, said master controller comprising: serial ports for serially receiving said clock, and, horizontal and vertical synchronization signals, respectively; and asymmetric-to-symmetric converter means for converting signals received through said serial ports into parallel format.

Claim 7

The timing controller of claim 1, said timing controller including latch circuitry for aiding in the synchronized release of signals from said timing generators.

Claim 8

The timing controller of claim 3, said auxiliary control means comprising: decoder logic.

Claim 9

The timing controller of claim 1, at least one of said timing generators comprising: control means having inputs receiving at least one of said synchronization signals and for synchronizing operation of said at least one timing generator with said at least one synchronization signal.

Claim 10

The timing controller of claim 2, said constant generator comprising: control means having inputs receiving at least one of said synchronization signals and for synchronizing operation of said constant generator with said at least one synchronization signal; said control means including a counter and counter control logic circuitry; said counter control logic circuitry providing counter control signals responsive to said at least one synchronization signal.

Claim 13

The method of claim 10, said video or image processing device including development system components, said output control signals comprising timing and control signals, step (f) including: providing said timing and control signals to said development system components.

Claim 14

The method of claim 10, said video or image processing device including a host computer interface logic, said method including prior to step (a): said incoming video or image signals with said host computer interface logic.

Claim 15

The method of claim 10, said video or image processing device including a TV system micro-controller, said method including prior to step (a): translating said incoming video or image signals with said TV system micro-controller.

Claim 16

The method of claim 10, step (a) including receiving said input signals in serial relation and converting said signals into parallel relation with said master controller; and said master controller outputting a series of control codes to a vertical timing generator, a horizontal timing generator, and an instruction.

Claim 17

The method of claim 10, said timing controller including a constant generator and an instruction generator, step (e) including generating respective control signals with said vertical or horizontal timing generator for said constant generator and said instruction generator, and, releasing said respective control signals in relation to said clock.

Claim 18

The method of claim 15, said output control signals including timing signals, step (f) including generating timing signals with said horizontal timing generator for said video or image processing device.

Claim 19

The method of claim 15, said output control signals including operating constants, step (f) including generating operating constants with said constant generator for said video or image processing device.

Claim 20

The method of claim 15, said output control signals including control instructions, step (f) including generating control instructions with said instruction generator for said video or image processing device.

Claim 21

The timing controller of claim 1, said master controller comprising a programmable state machine.

Claim 22

The timing controller of claim 1, said master controller including a set of registers; first multiplexer; mask enable logic; second multiplexer; program address counter; and program memory; said set of registers storing data and clock information obtained from said data and clock signals and loading said information into said first multiplexer; said first multiplexer providing said information from said set of registers to said second multiplexer and mask enable logic; said second multiplexer providing said information to said address counter; said address counter addressing locations in said program memory sequentially or by jump responsive to said information and said mask enable logic; said program memory outputting program signals containing address and operational mode instructions for said generators.

Claim 23

The timing controller of claim 20, said master controller including return register; said return register receiving address signals from said address counter for call operations and looping said address signals to said second multiplexer.

Claim 24

The timing controller of claim 20, said master controller including instruction decoder; said instruction decoder decoding a portion of said program signals and providing operation control signals to said second multiplexer and address counter.

Claim 25

The timing controller of claim 20, said program memory of said master controller providing a portion of said program signals to said first and second multiplexer.

Claim 26

The timing controller of claim 20, said first multiplexer of said master controller including synchronization means for synchronizing operations between at least two video or image processing devices.

Claim 27

The timing controller of claim 1, said first signals including field or frame rate control signals, vertical timing generator mode signals, and, horizontal timing generator mode signals.

Claim 28

The timing controller of claim 1, said timing generators comprising vertical and horizontal timing generators; said master controller controlling field or frame rate, and mode of operation of said vertical and horizontal timing generators.

Claim 29

The timing controller of claim 1, at least one of said generators including: nested memory means for accessing and sending a subset of a set of loop memory information responsive to each of a sequence of sequential memory instructions; and latch means for latching accessed of said subset of loop memory information in relation to said clock signal.

Claim 30

A timing controller for generating output signals including control and timing signals for a video or image processing device responsive to input signals including clock, horizontal synchronization, and vertical synchronization signals extracted from incoming video signals, said timing controller comprising: a master controller and at least two timing generators; said master controller generating first signals responsive to said input signals, providing said first signals to a first of said timing generators, and, together with said first generator, providing second signals to a second of said timing generators; said first generator generating third signals responsive to said first signals; said third signals including a part of said second signals; said second generator providing fourth signals responsive to said second signals; said fourth signals including a portion of said output signals and being synchronized with said horizontal and vertical synchronization signals; at least one of said generators including: a nested memory for accessing and sending a subset of a set of loop memory information responsive to each of a sequence of sequential memory instructions; and a latch for latching access of said subset of loop memory information in relation to said clock signal; said nested memory including: sequence counter; sequence memory; and repeat counter and control logic; said sequence counter including a control input for receiving a control mode signal from said master controller, said control mode signal interpretable as a starting sequence address; a said sequence counter including a sequence output for sequentially providing sequence addresses commencing with said starting sequence address to said sequence memory; said sequence memory including sequentially addressable locations storing said sequence of sequential memory instructions including timing information and releasing each in a subset of said sequential memory instructions responsive to said sequence counter; said sequential memory instructions including repeat address information; said sequence memory including a repeat output for sending said repeat address information to said repeat counter; said repeat counter and control logic including a repeat sequence output for signalling said sequence memory to re-release a selected of said sequential memory instructions responsive to said repeat address information; said repeat counter and control logic including a next output for signalling said sequence counter to provide a next of said sequence addresses.

Claim 31

A timing controller for generating output signals including control and timing signals for a video or image processing device responsive to input signals including clock, horizontal synchronization, and vertical synchronization signals extracted from incoming video signals, said timing controller comprising: a master controller and at least two timing generators; said master controller generating first signals responsive to said input signals, providing said first signals to a first of said timing generators, and, together with said first generator, providing second signals to a second of said timing generators; said first generator generating third signals responsive to said first signals; said third signals including a part of said second signals; said second generator providing fourth signals responsive to said second signals; said fourth signals including a portion of said output signals and being synchronized with said horizontal and vertical synchronization signals; at least one of said generators including: a nested memory for accessing and sending a subset of a set of loop memory information responsive to each of a sequence of sequential memory instructions; and a latch for latching access of said subset of loop memory information in relation to said clock signal; said nested memory including: sequence counter; sequence memory; and repeat counter and control logic; said sequence counter including a control input for receiving a control mode signal from said master controller, said control mode signal interpretable as a starting sequence address; a said sequence counter including a sequence output for sequentially providing sequence addresses commencing with said starting sequence address to said sequence memory; said sequence memory including sequentially addressable locations storing said sequence of sequential memory instructions including timing information and releasing each in a subset of said sequential memory instructions responsive to said sequence counter; said sequential memory instructions including repeat address information; said sequence memory including a repeat output for sending said repeat address information to said repeat counter; said repeat counter and control logic including a repeat sequence output for signalling said sequence memory to re-release a selected of said sequential memory instructions responsive to said repeat address information; said repeat counter and control logic including a next output for signalling said sequence counter to provide a next of said sequence addresses.

Claim 32

The timing controller of claim 28, said nested memory means including: loop counter; and, loop memory; said sequence memory sending a loop control signal to said loop counter; said loop control signal interpretable as a starting loop address to said loop memory; said loop counter including a loop counter output for sequentially providing loop addresses commencing with said starting loop address to said loop memory; said loop memory including sequentially addressable locations storing said set of loop memory information including loop patterns or programs; said loop memory including loop memory output for sending said loop memory information to said latch; said repeat counter and control logic including a second next output for signalling said loop counter to provide a next of said loop addresses; said loop memory information including an end of loop signal; said loop memory including an end output for sending said end of loop signal to said repeat counter causing said repeat counter to signal said sequence counter to provide a next of said sequence addresses.

Claim 33

The timing controller of claim 28, said one generator comprising a vertical timing generator.

Claim 34

The timing controller of claim 30, said vertical timing generator including a register load sequencer; said nested memory means including means for sending latch control signals to said register load sequencer; said register load sequencer in communicating relation with said latch means and including a clock to control latching; said register load sequencer including increment loop signal means for signalling said nested memory means to send a next in said subset of loop memory information.

Claim 35

The timing controller of claim 30, said generators including a horizontal timing, constant, and instruction generator; said loop memory information including mode control signals for said horizontal timing, constant, and instruction generators.

Claim 36

The timing controller of claim 32, said timing information including information for initializing and synchronizing operations of said horizontal timing, constant, and instruction generators.

Claim 37

The timing controller of claim 28, said nested memory means comprising random access memory, read only memory, or programmable logic arrays.

Claim 38

The timing controller of claim 28, said one generator comprising a constant generator.

Claim 39

The timing controller of claim 28, said one generator comprising a horizontal timing generator.

Claim 40

The timing controller of claim 1, said second generator comprising a horizontal timing generator; said fourth signals including said timing signals.

Claim 41

The timing controller of claim 28, said second generator comprising an instruction generator; said fourth signals including a portion of said control signals.

Claim 42

The timing controller of claim 28, said first generator providing fifth and sixth signals to a third and fourth of said timing generators.

Claim 43

The timing controller of claim 39, said fifth generator comprising a constant generator providing operating constants to said video or processing device; said sixth generator comprising an instruction generator providing a portion of said control signals to said video or image processing device.

Claim 44

The timing controller of claim 40, said first generator comprising a vertical timing generator; said second generator comprising a horizontal timing generator; said fourth signals including a portion of said timing signals.