DMA controller having multiple channels and buffer pool having plurality of buffers accessible to each channel for buffering data transferred to and from host computer

Claim 2

A computer system having multi-channel direct memory access (DMA), comprising: a host computer having a processor that runs software and a main memory; a system interface bus coupling the host computer and the main memory; a multi-channel DMA controller arrangement coupled to the system interface bus and having multiple input/output (I/O) channels; and a common buffer pool having a plurality of buffers accessible to each of the multiple channels for buffering data transferred to or from the host computer.

Claim 3

The system of claim 1, further comprising a status queue having a plurality of entries, with each entry in the status queue corresponding to a different one of the plurality of buffers and providing an indication as to whether the corresponding buffer is a free buffer available for use by one of the channels.

Claim 4

The system of claim 2, wherein entries for free buffers are non-contiguous entries within the status queue such that free buffer entries embedded in the status queue are identifiable and available for use by one of the channels.

Claim 5

The system of claim 3, wherein the DMA controller arrangement includes a controller mechanism for writing an in-use status in an entry in the status queue when one of the channels has claimed the entry in the status queue and the free buffer corresponding to the claimed entry in the status queue, the in-use status preventing other channels from claiming the entry in the status queue and the corresponding buffer.

Claim 6

The system of claim 4, wherein the DMA controller arrangement further includes a controller mechanism for writing a complete status in an entry in the status queue when the channel has received a packet of data in the corresponding buffer.

Claim 7

The system of claim 5, wherein the host computer includes a controller mechanism for clearing an entry in the status queue to make the entry in the status queue and the corresponding buffer available for use by one of the channels.

Claim 8

A computer system having multi-channel direct memory access (DMA), comprising: a host computer having a processor that runs software and a main memory connected to the processor for storing the software; a system interface bus coupling the host computer and the main memory; a multi-channel DMA controller arrangement coupled to the system interface bus and having multiple input/output (I/O) channels; and a common buffer pool having a plurality of buffers accessible to each of the multiple channels for buffering data transferred to or from the host computer, and further comprising: a status Queue having a plurality of entries, with each entry in the status queue corresponding to a different one of the plurality of buffers and providing an indication as to whether the corresponding buffer is a free buffer available for use by one of the channels, wherein entries for free buffers are non-contiguous entries within the status queue such that embedded free buffer entries in the status queue are identifiable and available for use by one of the channels, and wherein the DMA controller arrangement includes a controller mechanism for writing an in-use status in an entry in the status queue when one of the channels has claimed the entry in the status queue and the free buffer corresponding to the claimed entry in the status queue, the in-use status preventing other channels from claiming the entry in the status queue and the corresponding buffer, and wherein the DMA controller arrangement further includes a controller mechanism for writing a complete status in an entry in the status queue when the channel has received a packet of data in a corresponding buffer, and wherein the host computer includes a process for clearing an entry in the status queue to make the entry in the status queue and the corresponding buffer available for use by one of the channels, further comprising: a counting arrangement that maintains a count of the number of entries in the status queue that have been written with either an in-use status or a complete status and a count of the number of entries in the status queue that have been cleared.

Claim 9

The system of claim 7, further comprising a controller mechanism for determining the number of free buffers as a function of said counts.

Claim 10

The system of claim 4, further comprising a pointer that points to the entry in the status queue of a next likely free buffer, the DMA controller arrangement including a controller mechanism for examining the entry in the status queue pointed to by the pointer when searching for a free buffer; and updating the pointer after claiming a free buffer.

Claim 11

The system of claim 2, further comprising a descriptor queue, with each entry in the descriptor queue in the set corresponding to a different one of the plurality of buffers and providing a starting address of the corresponding buffer.

Claim 12

The system of claim 10, wherein the status queue and the descriptor queue correspond to the same buffers such that the DMA controller arrangement includes a controller mechanism for examining the status queue to identify a free buffer and obtaining the starting address or the free buffer from the descriptor queue.

Claim 14

The method of claim 12, further comprising arbitrating among the DMA channels for a right to access the status queue and claim a free buffer.

Claim 15

The method of claim 13, further comprising preventing a DMA channel that has been granted the right from obtaining the right again until after the other DMA channels have had an opportunity to obtain the right.

Claim 16

The method of claim 14, wherein the step of maintaining the status queue includes writing an in-use status in an entry in the status queue when one of the DMA channels has claimed the entry in the status queue and the free buffer corresponding to the claimed entry in the status queue, the in-use status preventing other DMA channels from claiming the entry in the status queue and the corresponding buffer.

Claim 17

The method of claim 15, wherein the step of maintaining the status queue includes writing a complete status in an entry in the status queue when the DMA channel has received a packet of data in the corresponding buffer.

Claim 18

The method of claim 16, wherein the step of maintaining includes clearing an entry in the status queue to make the entry in the status queue and the corresponding buffer available for use by one of the DMA channels.

Claim 20

The method of claim 18, further comprising determining the number of free buffers as a function of said counts.

Claim 21

The method of claim 17, further comprising maintaining a pointer that points to the entry in the status queue of a next likely free buffer, examining the entry in the status queue pointed to by the pointer when searching for a free buffer, and updating the pointer after claiming a free buffer.

Claim 22

The method of claim 20, further comprising maintaining a descriptor queue, with each entry in the descriptor queue corresponding to a different one of the plurality of buffers and providing a starting address of the corresponding buffer.

Claim 23

The method of claim 21, wherein the status queue and the descriptor queue correspond to the same buffers, and the step of determining the starting address includes examining the status queue to identify a free buffer and obtaining the starting address of the free buffer from the descriptor queue.

Claim 24

A multi-channel direct memory access (DMA) controller arrangement that controls DMA with a host computer, comprising: a multi-channel DMA controller arrangement having multiple input/output (I/O) channels; and a common buffer pool having a plurality of buffers accessible to each of the multiple channels for buffering data transferred to or from the host computer.

Claim 25

A multi-channel direct memory access (DMA) controller arrangement that controls DMA with a host computer, comprising: a multi-channel DMA controller arrangement having multiple input/output (I/O) channels; and a common buffer pool having a plurality of buffers accessible to each of the multiple channels for buffering data transferred to or from the host computer.

Claim 26

The DMA controller arrangement of claim 23, further comprising a status queue, with each entry in the status queue corresponding to a different one of the plurality of buffers and providing an indication as to whether the corresponding buffer is a free buffer available for use by one of the channels.

Claim 27

The DMA controller arrangement of claim 24, wherein entries for free buffers are non-contiguous entries within the status queue such that embedded free buffer entries in the status queue are identifiable and available for use by one of the channels.

Claim 28

The DMA controller arrangement of claim 25, wherein the DMA controller arrangement includes a controller mechanism for writing an in-use status in an entry in the status queue when one of the channels has claimed the entry in the status queue and the free buffer corresponding to the claimed entry in the status queue, the in-use status preventing other channels from claiming the entry in the status queue and the corresponding buffer.

Claim 29

The DMA controller arrangement of claim 26, wherein the controller mechanism writes a complete status in an entry in the status queue when the channel has received a packet of data in the corresponding buffer.

Claim 30

A multi-channel direct memory access (DMA) controller arrangement that controls DMA with a host computer, comprising: a multi-channel DMA controller arrangement having multiple input/out-out (I/O) channels; and a common buffer pool having a plurality of buffers accessible to each of the multiple channels for buffering data transferred to or from the host computer, further comprising: a status queue, with each entry in the status queue corresponding to a different one of the plurality of buffers and providing an indication as to whether the corresponding buffer is a free buffer available for use by one of the channels, wherein entries for free buffers are non-contiguous entries within the status queue such that embedded free buffer entries in the status queue are identifiable and available for use by one of the channels, wherein the DMA controller arrangement includes a controller mechanism for writing an in-use status in an entry in the status queue when one of the channels has claimed the entry in the status queue and the free buffer corresponding to the claimed entry in the status queue, the in-use status preventing other channels from claiming the entry in the status queue and the corresponding buffer, and wherein the controller mechanism writes a complete status in an entry in the status queue when the channel has received a packet of data in the corresponding buffer, and a counting arrangement that maintains a count of the number of entries in the status queue that have been written with either an in-use status or a complete status and a count of the number of entries in the status queue that have been cleared.

Claim 31

The DMA controller arrangement of claim 28, further comprising the controller mechanism determines the number of free buffers as a function of said counts.

Claim 32

The DMA controller arrangement of claim 29, further comprising a pointer that points to the entry in the status queue of a next likely free buffer, in which the controller mechanism examines the entry in the status queue pointed to by the pointer when searching for a free buffer, and updating the pointer after claiming a free buffer.

Claim 33

The DMA controller arrangement of claim 30, further comprising a descriptor queue, with each entry in the descriptor queue corresponding to a different one of the plurality of buffers and providing a starting address of the corresponding buffer.

Claim 34

The DMA controller arrangement of claim 31, wherein the status queue and the descriptor queue correspond to the same buffers such that the controller mechanism examines the status queue to identify a free buffer and obtaining the starting address of the free buffer from the descriptor queue.