Abstract A Verilog simulation method significantly reduces scenario execution time of very large scale integrated (VLSI) logic models that contain high numbers of sequential devices. A computer implemented method saves the state of sequential devices into a file at a chosen point in a simulation scenario and then inputs this file to initialize another simulation scenario. The method has the ability to utilize the user defined primitive (UDP) model data for the sequential devices present in the technology library. However, using the standard data structure available in the programming language interface (PLI), it is not possible to uniquely identify individual UDPs. UDPs have the characteristic of having only one output each. Therefore, it is possible to uniquely identify each UDP by the net name which is connected to this output. An exception to this is the situation where two or more like-named UDP outputs are connected to the same net. This is not considered a problem to this implementation, since the simulation execution will resolve the nets to one value (no checking is required).
A computer implemented method for saving turn-around-time in simulation of complex very large scale integrated (VLSI) circuit designs and quickly initializing sequential elements in Verilog simulation without the use of a scanning function of scannable sequential elements or complex initialization sequences, comprising steps of: running a Verilog simulation tool for a VLSI circuit design for a first simulation scenario; saving simulation states of sequential devices in said VLSI circuit design for said first simulation scenario; restoring the saved simulation states to the sequential devices for a second simulation scenario; and running the Verilog simulation tool for the VLSI circuit design for the second simulation scenario using the saved and restored simulation states from the first simulation scenario.
Claim 2
Dependent Claim
117 words
A computer implemented method for saving turn-around-time in simulation of complex very large scale integrated (VLSI) circuit designs and quickly initializing sequential elements in Verilog simulation without the use of a scanning function of scannable sequential elements or complex initialization sequences, comprising steps of: running a Verilog simulation tool for a VLSI circuit design for a first simulation scenario; saving simulation states of sequential devices in said VLSI circuit design for said first simulation scenario; restoring the saved simulation states to the sequential devices for a second simulation scenario; and running the Verilog simulation tool for the VLSI circuit design for the second simulation scenario using the saved and restored simulation states from the first simulation scenario.
Claim 3
Dependent Claim
61 words
A computer implemented method according to claim 1, further comprising the step of changing at least one of the saved states for sequential devices in said VLSI circuit design, and wherein said step of running the Verilog simulation tool for the VLSI circuit design for the second scenario uses the saved and the changed simulation states from the first simulation scenario.
Claim 4
Dependent Claim
49 words
The computer implemented method recited in claim 1 further comprising the step of uniquely identifying user defined primitives (UDPs) for the purpose of retrieving and storing current states of UDPs, said step of uniquely identifying being performed using the output net name of the UDP to uniquely identify it.
Claim 5
Dependent Claim
60 words
A computer implemented method according to claim 1, further comprising the step of preassigning at least one of the states for sequential devices in said VLSI circuit design, and wherein said step of running the Verilog simulation tool for the VLSI circuit design for the second scenario uses the saved and the preassigned simulation states from the first simulation scenario.