US5787006A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for management of integrated circuit layout verification processes
Assignee: Micron Technology Inc
•
Filing: 1996-04-30
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Granted: 1998-07-28
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Expires: 2016-04-30
Abstract
Abstract An apparatus and method for managing data obtained during the Design Rule Check (DRC) and Layout versus Schematic (LVS) verification procedures executed during the design of an integrated circuit. The apparatus is a data processing system which includes a database containing information regarding the schematics and layouts of the cells of an integrated circuit. The system accesses the database upon the completion of a DRC or LVS operation and queries the user as to whether the cell should be marked as successfully passing the appropriate verification procedure. A user is also able to access a report generating module to inspect the verification status of a cell in the IC design and generate a report showing the status of the verification procedures for each cell, organized according to one of several criteria.
Inventors
- 👤 Christophe J. Chevallier
- 👤 Yarema A. Hryciw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:22
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
146 words
A data processing system for use in managing and analyzing data generated during the design of an integrated circuit or an electronic system mounted on a printed circuit board, comprising: a database containing layout data files for a plurality of cells of the integrated circuit or system, the layout data file for each cell containing a time of the last modification of the layout for that cell; an input device for allowing a user to designate a cell and its corresponding data files contained in the database; design rule checking means for performing a design rule verification process on a layout data file of the designated cell; and a data processor capable of accessing the layout data file corresponding to the designated cell and modifying that file by appending a time of a successful completion of the design rule verification process to the layout data file.
Claim 2
Dependent Claim
146 words
A data processing system for use in managing and analyzing data generated during the design of an integrated circuit or an electronic system mounted on a printed circuit board, comprising: a database containing layout data files for a plurality of cells of the integrated circuit or system, the layout data file for each cell containing a time of the last modification of the layout for that cell; an input device for allowing a user to designate a cell and its corresponding data files contained in the database; design rule checking means for performing a design rule verification process on a layout data file of the designated cell; and a data processor capable of accessing the layout data file corresponding to the designated cell and modifying that file by appending a time of a successful completion of the design rule verification process to the layout data file.
Claim 3
Dependent Claim
68 words
The data processing system of claim 1, further comprising: a second data processor capable of accessing the modified layout data file corresponding to the designated cell and storing the time of the last modification of the layout and the appended time of successful completion of the design rule verification process, and for processing the stored data to determine the time between the events corresponding to the stored data.
Claim 4
Dependent Claim
23 words
The data processing system of claim 2, further comprising: a report generator for generating a report showing the results of processing the data.
Claim 5
Dependent Claim
30 words
The data processing system of claim 1, wherein the data processor appends the time of the successful completion of the design rule verification process in response to a user command.
Claim 6
Dependent Claim
35 words
The data processing system of claim 1, wherein the data processor automatically appends the time of the successful completion of the design rule verification process when no errors are found upon completion of the process.
Claim 7
Dependent Claim
72 words
The data processing system of claim 1, wherein the layout data file for the designated cell includes a reference to a layout data file for a second cell, and further, wherein the data processor is capable of accessing the layout file for the second file and modifying that file by appending a time of a successful completion of the design rule verification process to the layout data file for the second cell.
Claim 8
Dependent Claim
178 words
A data processing system for use in managing and analyzing data generated during the design of an integrated circuit or an electronic system mounted on a printed circuit board, comprising: a database containing schematic and layout data files for a plurality of cells of the integrated circuit or system, the schematic data file for each cell containing a time of the last modification of the schematic for that cell and the layout data file for each cell containing a time of the last modification of the layout for that cell; an input device for allowing a user to designate a cell and its corresponding data files contained in the database; layout versus schematic verification means for performing a layout versus schematic verification process on a layout data file and its corresponding schematic data file of the designated cell; and a data processor capable of accessing the layout data file corresponding to the designated cell and modifying that file by appending a time of a successful completion of the layout versus schematic verification process to the layout data file.
Claim 9
Dependent Claim
178 words
A data processing system for use in managing and analyzing data generated during the design of an integrated circuit or an electronic system mounted on a printed circuit board, comprising: a database containing schematic and layout data files for a plurality of cells of the integrated circuit or system, the schematic data file for each cell containing a time of the last modification of the schematic for that cell and the layout data file for each cell containing a time of the last modification of the layout for that cell; an input device for allowing a user to designate a cell and its corresponding data files contained in the database; layout versus schematic verification means for performing a layout versus schematic verification process on a layout data file and its corresponding schematic data file of the designated cell; and a data processor capable of accessing the layout data file corresponding to the designated cell and modifying that file by appending a time of a successful completion of the layout versus schematic verification process to the layout data file.
Claim 10
Dependent Claim
73 words
The data processing system of claim 7, further comprising: a second data processor capable of accessing the schematic and modified layout data files corresponding to the designated cell and storing the time of the last modification of the schematic and layout and the appended time of successful completion of the layout versus schematic verification process, and for processing the stored data to determine the time between the events corresponding to the stored data.
Claim 11
Dependent Claim
23 words
The data processing system of claim 8, further comprising: a report generator for generating a report showing the results of processing the data.
Claim 12
Dependent Claim
36 words
The data processing system of claim 7, wherein the data processor automatically appends the time of the successful completion of the layout versus schematic verification process when no errors are found upon completion of the process.
Claim 13
Dependent Claim
31 words
The data processing system of claim 7, wherein the data processor appends the time of the successful completion of the layout versus schematic verification process in response to a user command.
Claim 14
Dependent Claim
73 words
The data processing system of claim 7, wherein the layout data file for the designated cell includes a reference to a layout data file for a second cell, and further, wherein the data processor is capable of accessing the layout file for the second file and modifying that file by appending a time of a successful completion of the layout versus schematic verification process to the layout data file for the second cell.
Claim 15
Dependent Claim
208 words
A data processing system for use in managing and analyzing data generated during the design of an integrated circuit or an electronic system mounted on a printed circuit board, comprising: a database containing schematic and layout data files for a plurality of cells of the integrated circuit or system, the schematic data file for each cell containing a time of the last modification of the schematic for that cell and the layout data file for each cell containing a time of the last modification of the layout for that cell; an input device for allowing a user to designate a cell and its corresponding data files contained in the database; design rule checking means for performing a design rule verification process on a layout data file of the designated cell; layout versus schematic verification means for performing a layout versus schematic verification process on a layout data file and its corresponding schematic data file of the designated cell; and a data processor capable of accessing the layout data file corresponding to the designated cell and modifying that file by appending a time of a successful completion of the design rule verification process and a successful completion of the layout versus schematic verification process to the layout data file.
Claim 16
Dependent Claim
208 words
A data processing system for use in managing and analyzing data generated during the design of an integrated circuit or an electronic system mounted on a printed circuit board, comprising: a database containing schematic and layout data files for a plurality of cells of the integrated circuit or system, the schematic data file for each cell containing a time of the last modification of the schematic for that cell and the layout data file for each cell containing a time of the last modification of the layout for that cell; an input device for allowing a user to designate a cell and its corresponding data files contained in the database; design rule checking means for performing a design rule verification process on a layout data file of the designated cell; layout versus schematic verification means for performing a layout versus schematic verification process on a layout data file and its corresponding schematic data file of the designated cell; and a data processor capable of accessing the layout data file corresponding to the designated cell and modifying that file by appending a time of a successful completion of the design rule verification process and a successful completion of the layout versus schematic verification process to the layout data file.
Claim 17
Dependent Claim
76 words
The data processing system of claim 13, further comprising: a second data processor capable of accessing the schematic and modified layout data files corresponding to the designated cell and storing the time of the last modification of the schematic and layout and the appended times of successful completion of the design rule and layout versus schematic verification processes, and for processing the stored data to determine the time between the events corresponding to the stored data.
Claim 18
Dependent Claim
33 words
The data processing system of claim 14, wherein the second data processor processes the data to determine the time between the last modification of the schematic and the last modification of the layout.
Claim 19
Dependent Claim
39 words
The data processing system of claim 14, wherein the second data processor processes the data to determine the time between the last modification of the layout and the time of the successful completion of the design rule verification process.
Claim 20
Dependent Claim
40 words
The data processing system of claim 14, wherein the second data processor processes the data to determine the time between the last modification of the layout and the time of the successful completion of the layout versus schematic verification process.
Claim 21
Dependent Claim
23 words
The data processing system of claim 14, further comprising: a report generator for generating a report showing the results of processing the data.
Claim 22
Dependent Claim
23 words
The data processing system of claim 18, further comprising: an output device for displaying the contents of the generated report to the user.
Claim 23
Dependent Claim
26 words
The data processing system of claim 18, wherein the report generator generates a report showing the output times sorted according to a name of the cell.
Claim 24
Dependent Claim
34 words
The data processing system of claim 13, wherein the data processor appends the time of the successful completion of the design rule and layout versus schematic verification processes in response to a user command.
Claim 25
Dependent Claim
39 words
The data processing system of claim 13, wherein the data processor automatically appends the time of the successful completion of the design rule and layout versus schematic verification processes when no errors are found upon completion of the processes.
Claim 26
Dependent Claim
83 words
The data processing system of claim 13, wherein the layout data file for the designated cell includes a reference to a layout data file for a second cell, and further, wherein the data processor is capable of accessing the layout file for the second file and modifying that file by appending a time of a successful completion of the design rule verification process and a successful completion of the layout versus schematic verification process to the layout data file for the second cell.
Claim 27
Independent Claim
119 words
A method of managing and analyzing data generated during the design of an integrated circuit or an electronic system, comprising: constructing a database containing layout data files for a plurality of cells of the integrated circuit or system, the layout data file for each cell containing a time of the last modification of the layout for that cell; designating a cell and its corresponding data files contained in the database; performing a design rule verification process on a layout data file of the designated cell; and accessing the layout data file corresponding to the designated cell and modifying that file by appending a time of a successful completion of the design rule verification process to the layout data file.
Claim 28
Independent Claim
119 words
A method of managing and analyzing data generated during the design of an integrated circuit or an electronic system, comprising: constructing a database containing layout data files for a plurality of cells of the integrated circuit or system, the layout data file for each cell containing a time of the last modification of the layout for that cell; designating a cell and its corresponding data files contained in the database; performing a design rule verification process on a layout data file of the designated cell; and accessing the layout data file corresponding to the designated cell and modifying that file by appending a time of a successful completion of the design rule verification process to the layout data file.
Claim 29
Dependent Claim
35 words
The method of claim 24, wherein the time of the successful completion of the design rule verification process is automatically appended to the data file when no errors are found upon completion of the process.
Claim 30
Dependent Claim
66 words
The method of claim 24, further comprising the steps of: accessing the modified layout data file corresponding to the designated cell and storing the time of the last modification of the layout and the appended time of successful completion of the design rule verification process in a storage device; and processing the stored data to output the time between the events corresponding to the stored data.
Claim 31
Dependent Claim
20 words
The method of claim 26, further comprising the step of: generating a report showing the results of processing the data.
Claim 32
Dependent Claim
30 words
The method of claim 24, wherein the time of the successful completion of the design rule verification process is appended to the data file in response to a user command.
Claim 33
Dependent Claim
70 words
The method of claim 24, wherein the layout data file for the designated cell includes a reference to a layout data file for a second cell, and further, wherein the method includes the step of: accessing the layout file for the second file and modifying that file by appending a time of a successful completion of the design rule verification process to the layout data file for the second cell.
Claim 34
Independent Claim
150 words
A method of managing and analyzing data generated during the design of an integrated circuit or an electronic system, comprising: constructing a database containing schematic and layout data files for a plurality of cells of the integrated circuit or system, the schematic data file for each cell containing a time of the last modification of the schematic for that cell, and the layout data file for each cell containing a time of the last modification of the layout for that cell; designating a cell and its corresponding data files contained in the database; performing a layout versus schematic verification process on a layout data file and its corresponding schematic data file of the designated cell; and accessing the layout data file corresponding to the designated cell and modifying that file by appending a time of a successful completion of the layout versus schematic verification process to the layout data file.
Claim 35
Independent Claim
150 words
A method of managing and analyzing data generated during the design of an integrated circuit or an electronic system, comprising: constructing a database containing schematic and layout data files for a plurality of cells of the integrated circuit or system, the schematic data file for each cell containing a time of the last modification of the schematic for that cell, and the layout data file for each cell containing a time of the last modification of the layout for that cell; designating a cell and its corresponding data files contained in the database; performing a layout versus schematic verification process on a layout data file and its corresponding schematic data file of the designated cell; and accessing the layout data file corresponding to the designated cell and modifying that file by appending a time of a successful completion of the layout versus schematic verification process to the layout data file.
Claim 36
Dependent Claim
71 words
The method of claim 30, further comprising the steps of: accessing the schematic and modified layout data files corresponding to the designated cell and storing the time of the last modification of the schematic and layout and the appended time of successful completion of the layout versus schematic verification process in a storage device; and processing the stored data to output the time between the events corresponding to the stored data.
Claim 37
Dependent Claim
20 words
The method of claim 30, further comprising the step of: generating a report showing the results of processing the data.
Claim 38
Dependent Claim
31 words
The method of claim 30, wherein the time of the successful completion of the layout versus schematic verification process is appended to the data file in response to a user command.
Claim 39
Dependent Claim
36 words
The method of claim 30, wherein the time of the successful completion of the layout versus schematic verification process is automatically appended to the data file when no errors are found upon completion of the process.
Claim 40
Dependent Claim
71 words
The method of claim 30, wherein the layout data file for the designated cell includes a reference to a layout data file for a second cell, and further, wherein the method includes the step of: accessing the layout file for the second file and modifying that file by appending a time of a successful completion of the layout versus schematic verification process to the layout data file for the second cell.
Claim 41
Independent Claim
248 words
A method of managing and analyzing data generated during the design of an integrated circuit or an electronic system, comprising: constructing a database containing schematic and layout data files for a plurality of cells of the integrated circuit or system, the schematic data file for each cell containing a time of the last modification of the schematic for that cell, and the layout data file for each cell containing a time of the last modification of the layout for that cell; designating a cell and its corresponding data files contained in the database; performing a design rule verification process on a layout data file of the designated cell; performing a layout versus schematic verification process on a layout data file and its corresponding schematic data file of the designated cell; accessing the layout data file corresponding to the designated cell and modifying that file by appending a time of a successful completion of the design rule verification process and a successful completion of the layout versus schematic verification process to the layout data file; accessing the schematic and modified layout data files corresponding to the designated cell and storing the time of the last modification of the schematic and layout and the appended times of successful completion of the design rule and layout versus schematic verification processes in a storage device; processing the stored data to output the time between the events corresponding to the stored data; and generating a report showing the results of processing the data.
Claim 42
Independent Claim
248 words
A method of managing and analyzing data generated during the design of an integrated circuit or an electronic system, comprising: constructing a database containing schematic and layout data files for a plurality of cells of the integrated circuit or system, the schematic data file for each cell containing a time of the last modification of the schematic for that cell, and the layout data file for each cell containing a time of the last modification of the layout for that cell; designating a cell and its corresponding data files contained in the database; performing a design rule verification process on a layout data file of the designated cell; performing a layout versus schematic verification process on a layout data file and its corresponding schematic data file of the designated cell; accessing the layout data file corresponding to the designated cell and modifying that file by appending a time of a successful completion of the design rule verification process and a successful completion of the layout versus schematic verification process to the layout data file; accessing the schematic and modified layout data files corresponding to the designated cell and storing the time of the last modification of the schematic and layout and the appended times of successful completion of the design rule and layout versus schematic verification processes in a storage device; processing the stored data to output the time between the events corresponding to the stored data; and generating a report showing the results of processing the data.
Claim 43
Dependent Claim
51 words
The method of claim 36, wherein the step of appending the time of the successful completion of the design rule verification process and the successful completion of the layout versus schematic verification process to the layout data file is performed automatically when no errors are found upon completion of the processes.
Claim 44
Dependent Claim
26 words
The method of claim 36, wherein the step of processing the stored data determines the time between the last modification of the schematic and the layout.
Claim 45
Dependent Claim
36 words
The method of claim 36, wherein the step of processing the stored data determines the time between the last modification of the layout and the time of the successful completion of the design rule verification process.
Claim 46
Dependent Claim
37 words
The method of claim 36, wherein the step of processing the stored data determines the time between the last modification of the layout and the time of the successful completion of the layout versus schematic verification process.
Claim 47
Dependent Claim
27 words
The method of claim 36, wherein the step of generating a report generates a report showing the output times sorted according to a name of the cell.
Claim 48
Dependent Claim
46 words
The method of claim 31, wherein the step of appending the time of the successful completion of the design rule verification process and the successful completion of the layout versus schematic verification process to the layout data file is performed in response to a user command.
Claim 49
Dependent Claim
81 words
The method of claim 36, wherein the layout data file for the designated cell includes a reference to a layout data file for a second cell, and further, wherein the method includes the step of: accessing the layout file for the second file and modifying that file by appending a time of a successful completion of the design rule verification process and a successful completion of the layout versus schematic verification process to the layout data file for the second cell.
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