US5793079A
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US
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Single transistor non-volatile electrically alterable semiconductor memory device
Assignee: Semiconductor Components Industries LLC
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Filing: 1996-07-22
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Granted: 1998-08-11
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Expires: 2016-07-22
Abstract
Abstract An electrically alterable semiconductor memory device having an array of memory cells formed by individual transistors. The structure of the memory cells is compact and facilitates high density memory devices and is particularly well suited for contactless, virtual ground arrays. The memory cells can be read and programmed a page at a time. The memory cells can also be programmed using source-side hot-electron injection with improved efficiency and lowered programming currents. In one embodiment, the structure of the memory cells include: a substrate having a diffused source region, a diffused drain region, and a channel region between the diffused source region and the diffused drain region; a select gate positioned adjacent to the channel region, the select gate being positioned over a first portion of the channel region, the first portion being adjacent to the diffused source region and extending therefrom towards the diffused drain region; a floating gate adjacent to the channel region, the floating gate being positioned over a second portion of the channel region, the second portion being adjacent to the diffused drain region and extending therefrom towards the diffused source region; and a control gate over the floating gate. By providing select gates in the memory cells, problematic reverse currents in adjacent unselected memory cells of a contactless, virtual ground array are blocked or prevented during programming. The invention also pertains to a method for fabricating the semiconductor memory device.
Inventors
- 👤 Sorin Georgescu
- 👤 Andrei Mihnea
- 👤 Radu Vanco
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:23
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0491; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
223 words
A programmable and erasable non-volatile memory device having a plurality of memory cells, said device comprising: a substrate having the memory cells formed thereon, said substrate having diffused source/drain regions parallel to one another in a first direction, and forming channel regions between adjacent pairs of the diffused source region and the diffused drain region; select gate traces positioned over each of the channel regions, said select gate traces being parallel to one another in the first direction, each of said select gate traces being positioned over a first portion of the corresponding channel region, the first portion of the corresponding channel region being adjacent to the corresponding diffused source region and extending therefrom towards the corresponding diffused drain region; floating gates for the memory cells, each of the memory cells including one of said floating gates, each of said floating gates being positioned over a second portion of the corresponding channel region, the second portion of the corresponding channel region being adjacent to the corresponding diffused drain region and extending therefrom towards the diffused source region; and wordline traces over each of said floating gates, each of said wordline traces being parallel to one another in a second direction, and each of said wordline traces being positioned over the corresponding floating gates and over a portion of the corresponding select gate traces.
Claim 2
Dependent Claim
223 words
A programmable and erasable non-volatile memory device having a plurality of memory cells, said device comprising: a substrate having the memory cells formed thereon, said substrate having diffused source/drain regions parallel to one another in a first direction, and forming channel regions between adjacent pairs of the diffused source region and the diffused drain region; select gate traces positioned over each of the channel regions, said select gate traces being parallel to one another in the first direction, each of said select gate traces being positioned over a first portion of the corresponding channel region, the first portion of the corresponding channel region being adjacent to the corresponding diffused source region and extending therefrom towards the corresponding diffused drain region; floating gates for the memory cells, each of the memory cells including one of said floating gates, each of said floating gates being positioned over a second portion of the corresponding channel region, the second portion of the corresponding channel region being adjacent to the corresponding diffused drain region and extending therefrom towards the diffused source region; and wordline traces over each of said floating gates, each of said wordline traces being parallel to one another in a second direction, and each of said wordline traces being positioned over the corresponding floating gates and over a portion of the corresponding select gate traces.
Claim 3
Dependent Claim
30 words
A programmable and erasable non-volatile memory device as recited in claim 1, wherein said device further comprises: a first dielectric layer positioned between said select gate traces and said substrate.
Claim 4
Dependent Claim
29 words
A programmable and erasable non-volatile memory device as recited in claim 2, wherein said device further comprises: a second dielectric layer positioned between said floating gate and said substrate.
Claim 5
Dependent Claim
52 words
A programmable and erasable non-volatile memory device as recited in claim 3, wherein said wordline traces are over said floating gates and over at least a portion of said select gate traces, and wherein said device further comprises: a third dielectric layer positioned between said select gate traces and said wordline traces.
Claim 6
Dependent Claim
30 words
A programmable and erasable non-volatile memory device as recited in claim 4, wherein said device further comprises: a fourth dielectric layer positioned between said floating gates and said wordline traces.
Claim 7
Dependent Claim
55 words
A programmable and erasable non-volatile memory device as recited in claim 1, wherein said device operates in a program mode, a read mode and an erase mode, and wherein in the program mode the memory cells are programmed by source-side hot-electron injection, and in the erase mode the memory cells are erased by Fowler-Nordheim tunneling.
Claim 8
Dependent Claim
43 words
A programmable and erasable non-volatile memory device as recited in claim 6, wherein, to access the memory cells in the read mode or the program mode, one of said wordline traces is selected and alternative ones of said select gate traces are activated.
Claim 9
Dependent Claim
53 words
A programmable and erasable non-volatile memory device as recited in claim 7, wherein each of said wordline traces is associated with a row of the memory cells, and wherein in the read mode or the program mode up to one-half the memory cells in a selected row can be simultaneously read or programmed.
Claim 10
Dependent Claim
39 words
A programmable and erasable non-volatile memory device as recited in claim 8, wherein one of an odd or even parity is selected, then the alternating ones of said select gate traces are selected in accordance with the selected parity.
Claim 11
Dependent Claim
45 words
A programmable and erasable non-volatile memory device as recited in claim 8, wherein the grounding of the alternative ones of said select gate traces not being selected operates to suppress current flow in a reverse direction through the unselected memory cells along the selected wordline.
Claim 12
Dependent Claim
43 words
A programmable and erasable non-volatile memory device as recited in claim 1, wherein each of said wordline traces positioned over the corresponding floating gates in the second direction make up control gates for each of the corresponding floating gates in the second direction.
Claim 13
Dependent Claim
78 words
A programmable and erasable non-volatile memory device as recited in claim 1, wherein said device operates in a program mode, a read mode and an erase mode, wherein, to access the memory cells in the read mode or the program mode, one of said wordline traces is selected, and alternative ones of said select gate traces are raised to a positive voltage potential and those of the select gate traces not receiving the positive voltage potential are grounded.
Claim 14
Dependent Claim
144 words
A programmable and erasable memory device having a plurality of memory cells formed by individual transistors, each of said memory cells comprising: a substrate having a diffused source region, a diffused drain region, and a channel region between the diffused source region and the diffused drain region; a select gate positioned adjacent to the channel region, said select gate being positioned over a first portion of the channel region, the first portion being adjacent to the diffused source region and extending therefrom towards the diffused drain region; a floating gate adjacent to the channel region, said floating gate being positioned over a second portion of the channel region, the second portion being adjacent to said diffused drain region and extending therefrom towards the diffused source region; and a control gate over said floating gate and over at least a portion of said select gate.
Claim 15
Dependent Claim
144 words
A programmable and erasable memory device having a plurality of memory cells formed by individual transistors, each of said memory cells comprising: a substrate having a diffused source region, a diffused drain region, and a channel region between the diffused source region and the diffused drain region; a select gate positioned adjacent to the channel region, said select gate being positioned over a first portion of the channel region, the first portion being adjacent to the diffused source region and extending therefrom towards the diffused drain region; a floating gate adjacent to the channel region, said floating gate being positioned over a second portion of the channel region, the second portion being adjacent to said diffused drain region and extending therefrom towards the diffused source region; and a control gate over said floating gate and over at least a portion of said select gate.
Claim 16
Dependent Claim
31 words
A programmable and erasable memory device as recited in claim 13, wherein said floating gate is also positioned over a portion of said select gate closest to the diffused drain region.
Claim 17
Dependent Claim
42 words
A programmable and erasable memory device as recited in claim 13, wherein each of said memory cells further comprises: a first dielectric layer between said select gate and said substrate; and a second dielectric layer between said floating gate and said substrate.
Claim 18
Dependent Claim
81 words
A programmable and erasable memory device as recited in claim 13, wherein said floating gate is also positioned over a portion of said select gate, and wherein each of said memory cells further comprises: a first dielectric layer between said select gate and said substrate; a second dielectric layer between said floating gate and said substrate; a third dielectric layer between said floating gate and said select gate; and a fourth dielectric layer between said control gate and said floating gate.
Claim 19
Dependent Claim
24 words
A programmable and erasable non-volatile memory device as recited in claim 1, wherein said select gate traces are entirely positioned over the channel regions.
Claim 20
Dependent Claim
36 words
A programmable and erasable non-volatile memory device as recited in claim 1, wherein said select gate traces are adjacent to and over the channel regions and are not formed over said floating gates or said wordlines.
Claim 21
Dependent Claim
31 words
A programmable and erasable non-volatile memory device as recited in claim 1, wherein said select gate traces include spacers alone the sides of said select gate traces in the first direction.
Claim 22
Dependent Claim
238 words
A programmable and erasable non-volatile memory device having a plurality of memory cells, said device comprising: a substrate having the memory cells formed thereon, said substrate having diffused source/drain regions parallel to one another in a first direction, and forming channel regions between adjacent pairs of the diffused source region and the diffused drain region; select gate traces positioned over each of the channel regions, said select gate traces being parallel to one another in the first direction, each of said select gate traces being positioned over a first portion of the corresponding channel region, the first portion of the corresponding channel region being adjacent to the corresponding diffused source region and extending therefrom towards the corresponding diffused drain region; floating gates for the memory cells, each of the memory cells including one of said floating gates, each of said floating gates being positioned over a second portion of the corresponding channel region, the second portion of the corresponding channel region being adjacent to the corresponding diffused drain region and extending therefrom towards the diffused source region, each of said floating gates also being positioned over a portion of said select gate traces closest to the diffused drain region; and wordline traces over each of said floating gates, each of said wordline traces being parallel to one another in a second direction, and each of said wordline traces being positioned over the corresponding floating-gates in the second direction.
Claim 23
Dependent Claim
238 words
A programmable and erasable non-volatile memory device having a plurality of memory cells, said device comprising: a substrate having the memory cells formed thereon, said substrate having diffused source/drain regions parallel to one another in a first direction, and forming channel regions between adjacent pairs of the diffused source region and the diffused drain region; select gate traces positioned over each of the channel regions, said select gate traces being parallel to one another in the first direction, each of said select gate traces being positioned over a first portion of the corresponding channel region, the first portion of the corresponding channel region being adjacent to the corresponding diffused source region and extending therefrom towards the corresponding diffused drain region; floating gates for the memory cells, each of the memory cells including one of said floating gates, each of said floating gates being positioned over a second portion of the corresponding channel region, the second portion of the corresponding channel region being adjacent to the corresponding diffused drain region and extending therefrom towards the diffused source region, each of said floating gates also being positioned over a portion of said select gate traces closest to the diffused drain region; and wordline traces over each of said floating gates, each of said wordline traces being parallel to one another in a second direction, and each of said wordline traces being positioned over the corresponding floating-gates in the second direction.
Claim 24
Dependent Claim
36 words
A programmable and erasable non-volatile memory device as recited in claim 20, wherein said select gate traces are adjacent to and over the channel regions and are not formed over said floating gates or said wordlines.
Claim 25
Dependent Claim
31 words
A programmable and erasable non-volatile memory device as recited in claim 20, wherein said select gate traces include spacers alone the sides of said select gate traces in the first direction.
Claim 26
Dependent Claim
27 words
A programmable and erasable non-volatile memory device as recited in claim 20, wherein said wordline traces are positioned over said floating gates and said select gate traces.
Claim 27
Dependent Claim
56 words
A programmable and erasable non-volatile memory device as recited in claim 23, wherein said select gate traces are adjacent to and over the channel regions and are not formed over said floating gates or said wordlines, and wherein said select gate traces include spacers alone the sides of said select gate traces in the first direction.
Claim 28
Dependent Claim
22 words
A programmable and erasable memory device as recited in claim 13, wherein said select gate is entirely positioned over the channel region.
Claim 29
Dependent Claim
35 words
A programmable and erasable memory device as recited in claim 13, wherein said select gate is adjacent to and over the channel region and are not formed over said floating gate or said control gate.
Claim 30
Dependent Claim
24 words
A programmable and erasable memory device as recited in claim 13, wherein said select gate include spacers alone the sides of said select gate.
Claim 31
Dependent Claim
176 words
A programmable and erasable memory device having a plurality of memory cells formed by individual transistors, each of said memory cells comprising: a substrate having a diffused source region, a diffused drain region, and a channel region between the diffused source region and the diffused drain region; a select gate positioned adjacent to the channel region, said select gate being positioned over a first portion of the channel region, the first portion being adjacent to the diffused source region and extending therefrom towards the diffused drain region; a floating gate adjacent to the channel region, said floating gate being positioned over a second portion of the channel region, the second portion being adjacent to said diffused drain region and extending therefrom towards the diffused source region, and said floating gate being positioned over a portion of said select gate closest to the diffused drain region; and a control gate over said floating gate, wherein said select gate is adjacent to and over the channel regions and not formed over said floating gate or said control gate.
Claim 32
Dependent Claim
176 words
A programmable and erasable memory device having a plurality of memory cells formed by individual transistors, each of said memory cells comprising: a substrate having a diffused source region, a diffused drain region, and a channel region between the diffused source region and the diffused drain region; a select gate positioned adjacent to the channel region, said select gate being positioned over a first portion of the channel region, the first portion being adjacent to the diffused source region and extending therefrom towards the diffused drain region; a floating gate adjacent to the channel region, said floating gate being positioned over a second portion of the channel region, the second portion being adjacent to said diffused drain region and extending therefrom towards the diffused source region, and said floating gate being positioned over a portion of said select gate closest to the diffused drain region; and a control gate over said floating gate, wherein said select gate is adjacent to and over the channel regions and not formed over said floating gate or said control gate.
Claim 33
Dependent Claim
24 words
A programmable and erasable memory device as recited in claim 28, wherein said select gate includes spacers alone the sides of said select gate.
Claim 34
Dependent Claim
25 words
A programmable and erasable memory device as recited in claim 28, wherein said control gate is positioned over said floating gate and said select gate.
Claim 35
Dependent Claim
24 words
A programmable and erasable memory device as recited in claim 30, wherein said select gate includes spacers alone the sides of said select gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-10 | 2002-02-09 | 2002-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-10 | 2006-02-09 | 2006-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-10 | 2010-02-09 | 2010-08-11 | $7700.00 | Window Closed / Lapsed |