US5793238A
Expired / Lapsed
US
⏱️ 0.0 years remaining
RC delay with feedback
Assignee: Callahan Cellular LLC
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Filing: 1996-11-01
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Granted: 1998-08-11
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Expires: 2016-11-01
Abstract
Abstract The present invention concerns a delay circuit that provides a fixed amount of delay that is generally independent of process variations. An input resistance is provided that may be presented to a threshold device, such as an inverter, that may then be presented as an output. The output of the threshold device may also be presented through a feedback path comprising a capacitive device to the input of the threshold device. The feedback through the capacitive load actively resists the movement of the load. As a result, the delay provided by the circuit is generally resistant to process variations.
Inventors
- 👤 William G. Baker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:09
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/133
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
104 words
A circuit for providing a delay between an input and an output comprising: a resistance circuit receiving said input; a threshold circuit configured to present said output in response to a threshold input received from said resistance circuit, wherein said output is delayed from said input; and a capacitance circuit comprising a first transistor having a gate configured to receive said output of said threshold circuit, a second transistor coupled between said first transistor and said threshold circuit, and a third transistor coupled between said first and second transistors and ground, said capacitance circuit configured to present a feedback output to the threshold circuit.
Claim 2
Dependent Claim
104 words
A circuit for providing a delay between an input and an output comprising: a resistance circuit receiving said input; a threshold circuit configured to present said output in response to a threshold input received from said resistance circuit, wherein said output is delayed from said input; and a capacitance circuit comprising a first transistor having a gate configured to receive said output of said threshold circuit, a second transistor coupled between said first transistor and said threshold circuit, and a third transistor coupled between said first and second transistors and ground, said capacitance circuit configured to present a feedback output to the threshold circuit.
Claim 3
Dependent Claim
25 words
The circuit according to claim 1 wherein said capacitance circuit creates a positive feedback between said output of said threshold circuit and said feedback output.
Claim 4
Dependent Claim
13 words
The circuit according to claim 1 wherein said resistance circuit comprises a resistor.
Claim 5
Dependent Claim
18 words
The circuit according to claim 1 wherein said resistance circuit comprises: (i) a driver and (ii) a resistor.
Claim 6
Dependent Claim
13 words
The circuit according to claim 1 wherein said threshold circuit comprises an inverter.
Claim 7
Dependent Claim
14 words
The circuit according to claim 1 wherein the threshold circuit comprises a Schmitt trigger.
Claim 8
Dependent Claim
15 words
The circuit according to claim 1 wherein said third transistor is configured as a capacitor.
Claim 9
Dependent Claim
33 words
The circuit according to claim 1 comprising: a fourth transistor coupled between said capacitance circuit and ground; and a fifth transistor coupled between said output of said threshold circuit and said threshold input.
Claim 10
Dependent Claim
25 words
The circuit according to claim 1 wherein: said first transistor and said second transistor are NMOS transistors; and said third transistor is a PMOS transistor.
Claim 11
Dependent Claim
35 words
The circuit according to claim 8 wherein: said third transistor reduces said feedback; said fourth transistor maintains an accurate delay at said output; and said fifth transistor maintains a fast edge transition at said output.
Claim 12
Dependent Claim
115 words
A circuit for providing a delay between an input and an output comprising: means for providing a resistance and for receiving said input; means for providing said output in response to a threshold input from said resistance means, wherein said output is delayed from said input; and means for providing a capacitance comprising a first transistor having a gate configured to receive said output, a second transistor coupled between said first transistor and said output threshold means, and a third transistor coupled between said first and second transistors and ground, said capacitance means having: (i) a feedback output presented to said output threshold means and (ii) a feedback input received from said output threshold means.
Claim 13
Dependent Claim
115 words
A circuit for providing a delay between an input and an output comprising: means for providing a resistance and for receiving said input; means for providing said output in response to a threshold input from said resistance means, wherein said output is delayed from said input; and means for providing a capacitance comprising a first transistor having a gate configured to receive said output, a second transistor coupled between said first transistor and said output threshold means, and a third transistor coupled between said first and second transistors and ground, said capacitance means having: (i) a feedback output presented to said output threshold means and (ii) a feedback input received from said output threshold means.
Claim 14
Dependent Claim
22 words
The circuit according to claim 11 wherein said capacitance means creates a positive feedback between said feedback input and said feedback output.
Claim 15
Dependent Claim
15 words
The circuit according to claim 11 wherein said third transistor is configured as a capacitor.
Claim 16
Dependent Claim
28 words
The circuit according to claim 11 wherein said output threshold means is selected from the group consisting of an inverter, a Schmitt trigger and a threshold triggered device.
Claim 17
Independent Claim
105 words
A method for providing a delay between an input and an output comprising the steps of: (A) passing said input through a resistance until a threshold voltage is applied to a threshold circuit; (B) presenting said output from said threshold circuit in response to said threshold voltage and a first transistor having a gate configured to receive said output from said threshold circuit, a second transistor coupled between said first transistor and said threshold circuit and a third transistor coupled between said first and second transistors and ground; and (C) coupling said output to said threshold circuit, wherein said output is delayed from said input.
Claim 18
Independent Claim
105 words
A method for providing a delay between an input and an output comprising the steps of: (A) passing said input through a resistance until a threshold voltage is applied to a threshold circuit; (B) presenting said output from said threshold circuit in response to said threshold voltage and a first transistor having a gate configured to receive said output from said threshold circuit, a second transistor coupled between said first transistor and said threshold circuit and a third transistor coupled between said first and second transistors and ground; and (C) coupling said output to said threshold circuit, wherein said output is delayed from said input.
Claim 19
Dependent Claim
21 words
The method according to claim 15 wherein step (C) further comprises: increasing the speed of an edge transition of said output.
Claim 20
Dependent Claim
22 words
The method according to claim 15 wherein step (B) further comprises: reducing said feedback to a level above said threshold circuit input.
Claim 21
Dependent Claim
25 words
The method according to claim 15 wherein step (C) further comprises: generating a capacitance at said threshold circuit input in response to said third transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-10 | 2002-02-09 | 2002-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-10 | 2006-02-09 | 2006-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-10 | 2010-02-09 | 2010-08-11 | $7700.00 | Window Closed / Lapsed |