Non-volatile semiconductor memory device having NAND structure cells

Claim 1

A flash EEPROM (electrically erasable programmable read-only memory) with NAND structure cells having a plurality of memory cell arrays formed respectively in at least first and second wells of one conductivity type in turn formed in the surface of a semiconductor substrate of opposite conductivity type, each said memory cell arrays having a plurality of memory cell transistors of said NAND structure cells arranged in parallel in column direction symmetrically with a predetermined line lying between said wells in row direction, each said memory cell transistors being capable of retaining in its floating gate hot electrons injected by the Fowler-Nordheim (F-N) tunnelling, source and drain of every two adjacent ones of said memory cell transistors being formed of a single highly doped diffusion region formed in said wells, control gates of corresponding ones of said memory cell transistors included respectively in said memory cell arrays being connected respectively to control gate lines lying in parallel in row direction to form word lines, first and second ends of each of said NAND structure cells being connected to source and drain respectively of first and second select transistors having control gates connected respectively to first and second select gate lines lying in parallel with said control gate lines, and drain and source respectively of said first and second select transistors of respective ones of said memory cell arrays being connected respectively to bit lines lying in parallel in column direction, characterized by further comprising: means connected to said control gate lines and responsive to row address signal designating selected one of said control gate lines for erasure of data stored in said memory cell transistors associated therewith, for generating erase control signal consisting of first voltage to be supplied to said selected one of said control gate lines and second voltage to be supplied to unselected ones of said control gate lines, said first voltage being sufficient to remove said electrons retained in said memory cell transistors associated with said selected control gate line and, wherein said erase control signal generating means comprises: a first portion responsive to less significant bits of said row address signal for providing decode outputs respectively for said control gate lines; and a second portion responsive to more significant bits of said row address signal for selectively allowing said decode outputs to be provided to said control gate lines of one of said first and second wells.