US5801094A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual damascene process
Assignee: United Microelectronics Corp
•
Filing: 1997-06-12
•
Granted: 1998-09-01
•
Expires: 2017-06-12
Abstract
Abstract A dual damascene process forms a two level metal interconnect structure by first providing a interlayer oxide over a device structure and covering the interlevel oxide layer with an etch stop layer. The etch stop layer is patterned to form openings corresponding to the pattern of the interconnects that are to be formed in the first level of the two level interconnect structure. After the etch stop layer is patterned, an intermetal oxide layer is provided over the etch stop layer. Because the etch stop layer is relatively thin, the topography formed on the surface of the intermetal oxide layer is relatively small. A photoresist mask is then provided over the intermetal oxide layer with openings in the mask exposing portions of the intermetal oxide layer in the pattern of the wiring lines to be provided in the second level of the interconnect structure. The intermetal oxide layer is etched and the etching process continues to form openings in the interlayer oxide where the interlayer oxide is exposed by the openings in the etch stop layer. Thus, in a single etching step, the openings for both the second level wiring lines and the first level interconnects are defined. Metal is then deposited over the structure and excess metal is removed by chemical mechanical polishing to define the two level interconnect structure.
Inventors
- 👤 Tri-Rung Yew
- 👤 Meng-Chang Liu
- 👤 Water Lur
- 👤 Shih-Wei Sun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:47
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/084; H10W20/086; H10W20/082
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
228 words
A method of making an integrated circuit having first level conductor structures and second level conductor structures, the method comprising: providing a substrate incorporating one or more integrated circuit devices; providing an interlayer dielectric layer over the substrate; providing an etch stop layer over the interlayer dielectric layer; patterning the etch stop layer to define openings in the patterned etch stop layer corresponding to positions where first level conductor structures are to be formed; providing an intermetal dielectric layer over the patterned etch stop layer; forming a second level mask over the intermetal dielectric layer, the second level mask having openings corresponding to positions where second level conductor structures are to be formed; etching through the openings in the second level mask to form second level conductor openings in the intermetal dielectric layer, and etching through the openings in the patterned etch stop layer to form first level conductor openings in the interlayer dielectric layer and to provide edges of the openings, in the patterned etch stop layer, with a tapered configuration, so that the openings in the patterned etch stop layer provide for a step-free transition between respective ones of the second level conductor openings in the intermetal dielectric layer and the first level conductor openings in the interlayer dielectric layer; and depositing metal into the second level conductor openings and into the first level conductor openings.
Claim 2
Independent Claim
228 words
A method of making an integrated circuit having first level conductor structures and second level conductor structures, the method comprising: providing a substrate incorporating one or more integrated circuit devices; providing an interlayer dielectric layer over the substrate; providing an etch stop layer over the interlayer dielectric layer; patterning the etch stop layer to define openings in the patterned etch stop layer corresponding to positions where first level conductor structures are to be formed; providing an intermetal dielectric layer over the patterned etch stop layer; forming a second level mask over the intermetal dielectric layer, the second level mask having openings corresponding to positions where second level conductor structures are to be formed; etching through the openings in the second level mask to form second level conductor openings in the intermetal dielectric layer, and etching through the openings in the patterned etch stop layer to form first level conductor openings in the interlayer dielectric layer and to provide edges of the openings, in the patterned etch stop layer, with a tapered configuration, so that the openings in the patterned etch stop layer provide for a step-free transition between respective ones of the second level conductor openings in the intermetal dielectric layer and the first level conductor openings in the interlayer dielectric layer; and depositing metal into the second level conductor openings and into the first level conductor openings.
Claim 3
Dependent Claim
29 words
The method of claim 1, further comprising removing metal from above the intermetal dielectric layer, leaving metal within the second level conductor openings and the first level conductor openings.
Claim 4
Dependent Claim
30 words
The method of claim 2, wherein the removing metal leaves metal plugs in the second level conductor openings having upper surfaces coplanar with surrounding portions of the intermetal dielectric layer.
Claim 5
Dependent Claim
22 words
The method of claim 3, wherein the removing metal leaves a planarized surface over the metal plugs and the intermetal dielectric layer.
Claim 6
Dependent Claim
15 words
The method of claim 4, wherein the removing metal includes chemical mechanical polishing or etching.
Claim 7
Dependent Claim
15 words
The method of claim 4, wherein the removing metal is accomplished by chemical mechanical polishing.
Claim 8
Dependent Claim
16 words
The method of claim 1, wherein the interlayer dielectric and the intermetal dielectric comprise silicon oxide.
Claim 9
Dependent Claim
13 words
The method of claim 7, wherein the etch stop layer comprises silicon nitride.
Claim 10
Dependent Claim
25 words
The method of claim 1, wherein the openings in the second level mask are larger across than the openings in the patterned etch stop layer.
Claim 11
Dependent Claim
21 words
The method of claim 1, wherein the patterned etch stop layer acts as a hard mask for etching the interlayer dielectric.
Claim 12
Dependent Claim
46 words
The method of claim 1, wherein the openings in the patterned etch stop layer are tapered so that an upper portion of the openings in the patterned etch stop layer is wider across than a lower portion of the openings in the patterned etch stop layer.
Claim 13
Dependent Claim
42 words
The method of claim 1, wherein the interlayer dielectric and the intermetal dielectric comprise silicon oxide, the etch stop layer comprises silicon nitride and the etch stop layer is in contact with both the interlayer dielectric layer and the intermetal dielectric layer.
References Cited (Backward Citations)
US4372034A
Cited
US4372034B1
Cited
US4560034A
Cited
US4789648A
Cited
JPH03268326A
Cited
US5246882A
Cited
US5466639A
Cited
US5635423A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |