Logic circuit and semiconductor device using it

Claim 2

A logic circuit comprising: an output line; a first switch having an end connected to the output line and another end connected to a power source potential; a second switch having an end connected to the output line and another end connected to a ground potential; and a switching/rectifying circuit, which has an end connected to the output line and another end connected to an intermediate power source potential, for switching/rectifying, in which said intermediate power source potential is higher than the ground potential and lower than the power source potential.

Claim 3

A logic circuit according to claim 1, wherein said switching/rectifying circuit includes a third switch and a rectifier connected in series.

Claim 4

A logic circuit according to claim 2, wherein said rectifier includes at least one of a pn-junction element and a MOS transistor, wherein said MOS transistor includes a gate connected to one of a drain and a source of said MOS transistor.

Claim 5

A logic circuit according to claim 1, further comprising a stabilizing capacitance connected to the intermediate power source potential.

Claim 6

A logic circuit according to claim 1, wherein said logic circuit is implemented on a semiconductor chip, said semiconductor chip including another circuit that generates the intermediate power source potential.

Claim 7

A logic circuit according to claim 1, wherein said logic circuit is implemented on a semiconductor chip, and wherein the intermediate power source potential is directly generated by an AC/DC converter not included in said semiconductor chip.

Claim 8

A logic circuit comprising: an output line; a first switch having an end connected to the output line and another end connected to a power source potential; a second switch having an end connected to the output line and another end connected to a ground potential; and a plurality of first and second switching/rectifying circuits, each of which has an end connected to the output line and another end connected in parallel to each of a plurality of intermediate power source potentials, respectively, which are different from each other and are higher than the ground potential and lower than the power source potential, wherein the first switching/rectifying circuits prespectively allow currents to flow when the potential of the output line is lower than associated ones of the intermediate power source potentials, and the second switching/rectifying circuits respectively allow currents to flow when the potential of the output line is higher than associated ones of the intermediate power source potentials.

Claim 9

A logic circuit comprising: an output line; a first switch having an end connected to the output line and another end connected to a power source potential; a second switch having an end connected to the output line and another end connected to a ground potential; and a plurality of first and second switching/rectifying circuits, each of which has an end connected to the output line and another end connected in parallel to each of a plurality of intermediate power source potentials, respectively, which are different from each other and are higher than the ground potential and lower than the power source potential, wherein the first switching/rectifying circuits prespectively allow currents to flow when the potential of the output line is lower than associated ones of the intermediate power source potentials, and the second switching/rectifying circuits respectively allow currents to flow when the potential of the output line is higher than associated ones of the intermediate power source potentials.

Claim 10

A logic circuit according to claim 7, wherein each of the first switching/rectifying circuits includes a third switch and a first rectifying circuit, and each of the second switching/rectifying circuits includes a fourth switch and a second rectifying circuit.

Claim 11

A logic circuit according to claim 8, wherein each of said first and second rectifying circuits includes at least one of a pn-junction element and a MOS transistor, wherein said MOS transistor includes a gate connected to one of a drain and a source of said MOS transistor.

Claim 12

A logic circuit according to claim 8, wherein the potential of the output line is within a range of the ground potential and the power source potential, when the potential of the output line falls from the power source potential to the ground potential, the fourth switches of the second switching/rectifying circuits are turned ON, one after another, in an order from the fourth switch of that second switching/rectifying circuit which is connected to the highest one of the plurality of intermediate power source potentials, and finally, the second switch is turned ON, and when the potential of the output line rises from the ground potential to the power source potential, the third switches of the first switching/rectifying circuits are turned ON, one after another, in an order from the third switch of that first switching/rectifying circuit which is connected to the lowest one of the plurality of intermediate power source potentials, and finally, the first switch is turned ON.

Claim 13

A logic circuit according to claim 10, wherein at least two of the first to fourth switches are simultaneously kept turned ON during operation to make the potential of the output line rise and fall.

Claim 14

A logic circuit according to claim 7, further comprising a stabilizing capacitance connected to at least one of the plurality of intermediate power source potentials.

Claim 15

A logic circuit according to claim 7, wherein said logic circuit is implemented on a semiconductor chip, said semiconductor chip including another circuit that generates at least one of the plurality of intermediate power source potentials.

Claim 16

A logic circuit according to claim 7, wherein said logic circuit is implemented on a semiconductor chip, and wherein at least one of the plurality of intermediate power source potentials is directly generated by an AC/DC converter not included in said semiconductor chip.

Claim 17

A semiconductor device comprising at least one of a clock generator and a data line, each of which uses the logic circuit according to claim 1.

Claim 18

A semiconductor device comprising at least one of a clock generator and a data line, each of which uses the logic circuit according to claim 7.