US5812842A
Expired / Lapsed
US
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Method for initializing and reprogramming a control operation feature of a memory device
Assignee: Round Rock Research LLC
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Filing: 1997-01-13
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Granted: 1998-09-22
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Expires: 2017-01-13
Abstract
Abstract A method for initially programming a synchronous dynamic random access memory (SDRAM) device to have a first control operating option in response to a first command and for reprogramming the SDRAM device to have a second control operating option in response to a second command without interrupting the active state of the memory array.
Inventors
- 👤 Brett Williams
- 👤 Scott Schaefer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C11/4072; G11C7/00; G11C7/10; G11C7/1015; G11C7/1045; G11C7/1072
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
204 words
A method for programming a memory device to have a control operation feature, the control operation feature having a plurality of control operating options, comprising the following steps: (a) applying a first command to a master control circuit of the memory device; (b) generating a first control signal in said master control circuit in response to said first command; (c) providing an operational code to said memory device, said operational code specifying a desired one of said plurality of control operating options; (d) programming said desired control operating option in response to said first control signal; (e) applying a second command to said master control circuit of the memory device; (f) generating a second control signal in said master control circuit in response to said second command; and (g) programming said control operation feature to have a further one of said plurality of control operating options in response to said second control signal and during an active non-idle state of an array of memory cells of the memory device, such that the array remains simultaneously active in response to an active internal row address signal while the control operation feature is programmed to have the further one of said plurality of control operating options.
Claim 2
Independent Claim
204 words
A method for programming a memory device to have a control operation feature, the control operation feature having a plurality of control operating options, comprising the following steps: (a) applying a first command to a master control circuit of the memory device; (b) generating a first control signal in said master control circuit in response to said first command; (c) providing an operational code to said memory device, said operational code specifying a desired one of said plurality of control operating options; (d) programming said desired control operating option in response to said first control signal; (e) applying a second command to said master control circuit of the memory device; (f) generating a second control signal in said master control circuit in response to said second command; and (g) programming said control operation feature to have a further one of said plurality of control operating options in response to said second control signal and during an active non-idle state of an array of memory cells of the memory device, such that the array remains simultaneously active in response to an active internal row address signal while the control operation feature is programmed to have the further one of said plurality of control operating options.
Claim 3
Dependent Claim
34 words
The method as specified in claim 1, further comprising performing said step of programming said desired control operating option in response to said first control signal during an idle state of the memory device.
Claim 4
Dependent Claim
51 words
The method as specified in claim 1, wherein said step of programming said control operation feature to have said further one of said plurality of control operating options in response to said second control signal comprises providing a further operational code to said memory device specifying said one control operating option.
Claim 5
Dependent Claim
23 words
The method as specified in claim 1, wherein said step of applying said first command comprises applying an external set mode register command.
Claim 6
Dependent Claim
36 words
The method of claim 4 wherein the step of applying the external set mode register command comprises applying active Chip Select, Row Address Strobe, Column Address Strobe, and Write Enable signals to the master control circuit.
Claim 7
Dependent Claim
23 words
The method as specified in claim 1, wherein said step of applying said second command comprises applying a column address strobe registration command.
Claim 8
Dependent Claim
38 words
The method of claim 6 wherein the step of applying the Column Address Strobe registration command comprises applying active Chip Select and Column Address Strobe signals and an inactive Row Address Strobe signal to said master control circuit.
Claim 9
Dependent Claim
21 words
The method as specified in claim 1, wherein said step of applying said second command comprises applying an activate row command.
Claim 10
Dependent Claim
38 words
The method of claim 8 wherein the step of applying the active row command comprises applying active Chip Select, Row Address Strobe, and Column Address Strobe signals and an inactive Write Enable signal to said master control circuit.
Claim 11
Dependent Claim
32 words
The method as specified in claim 1, wherein said further one of said plurality of control operating options and said desired one of said plurality of control operating options are the same.
Claim 12
Dependent Claim
45 words
The method of claim 1 wherein the step of generating the first control signal in said master control circuit in response to said first command comprises generating an internal set mode register command signal in said master control circuit in response to said first command.
Claim 13
Dependent Claim
65 words
The method of claim 1 wherein the step of generating the first control signal in said master control circuit in response to said first command comprises generating the first control signal in said master control circuit in response to said first command and in response to an internal control state machine of the master control circuit indicating the memory device is in an idle state.
Claim 14
Dependent Claim
40 words
The method of claim 1 wherein the step of providing an operational code to said memory device comprises providing an operational code associated with a control operation feature selected from a group comprising burst length, burst type, and read latency.
Claim 15
Dependent Claim
37 words
The method of claim 13 wherein the step of providing an operational code associated with a control operation feature comprises providing an operational code specifying a burst length of one of two, four, and eight memory cycles.
Claim 16
Dependent Claim
34 words
The method of claim 13 wherein the step of providing an operational code associated with a control operation feature comprises providing an operational code specifying a burst type of one of sequential and interleaved.
Claim 17
Dependent Claim
37 words
The method of claim 13 wherein the step of providing an operational code associated with a control operation feature comprises providing an operational code specifying a read latency of one of one, two, and three clock cycles.
Claim 18
Dependent Claim
27 words
The method of claim 1 wherein the step of providing an operational code comprises providing an operational code to a D-flip-flop mode register in said memory device.
Claim 19
Dependent Claim
62 words
The method of claim 17 wherein the step of programming said desired control operating option in response to said first control signal comprises: a) latching said operational code through said D-flip-flop mode register in response to said first control signal; and b) programming said desired control operating option in accordance with said latched operational code in response to said first control signal.
Claim 20
Dependent Claim
43 words
The method of claim 1 wherein the step of generating the second control signal in said master control circuit in response to said second command comprises generating an internal toggle control signal in said master control circuit in response to said second command.
Claim 21
Dependent Claim
65 words
The method of claim 1 wherein the step of generating the second control signal in said master control circuit in response to said second command comprises generating the second control signal in said master control circuit in response to said second command and in response to an internal control state machine of the master control circuit indicating the memory device is in an active state.
Claim 22
Dependent Claim
45 words
The method of claim 1 wherein the step of generating the second control signal in said master control circuit in response to said second command comprises generating an internal column address strobe registration signal in said master control circuit in response to said second command.
Claim 23
Dependent Claim
92 words
The method of claim 1 wherein the step of programming said control operation feature to have a further one of said plurality of control operating options in response to said second control signal comprises: a) latching an operational code associated with said further one of said control operating options through a D-flip-flop mode register in said memory device in response to said second control signal; and b) programming said further one of said plurality of control operating options in accordance with said latched operational code in response to said second control signal.
Claim 24
Independent Claim
205 words
A method for programming a memory device to have a control operation feature, the control operation feature having a plurality of control operating options, comprising the following steps: (a) applying a first command to a master control circuit of the memory device; (b) generating a first control signal in said master control circuit in response to said first command; (c) providing an operational code to said memory device, said operational code specifying a desired one of said plurality of control operating options; (d) programming said desired control operating option in response to said first control signal; (e) applying a second command to said master control circuit of the memory device; (f) generating a second control signal in said master control circuit in response to said second command; and (g) toggling from said desired control operating option to a further one of said plurality of control operating options in response to said second control signal and during an active non-idle state of an array of memory cells of the memory device, such that the array remains simultaneously active in response to an active internal row address signal while the control operating option is programmed to have the further one of said plurality of control operating options.
Claim 25
Independent Claim
205 words
A method for programming a memory device to have a control operation feature, the control operation feature having a plurality of control operating options, comprising the following steps: (a) applying a first command to a master control circuit of the memory device; (b) generating a first control signal in said master control circuit in response to said first command; (c) providing an operational code to said memory device, said operational code specifying a desired one of said plurality of control operating options; (d) programming said desired control operating option in response to said first control signal; (e) applying a second command to said master control circuit of the memory device; (f) generating a second control signal in said master control circuit in response to said second command; and (g) toggling from said desired control operating option to a further one of said plurality of control operating options in response to said second control signal and during an active non-idle state of an array of memory cells of the memory device, such that the array remains simultaneously active in response to an active internal row address signal while the control operating option is programmed to have the further one of said plurality of control operating options.
Claim 26
Independent Claim
221 words
A method for programming a memory device to have a control operation feature, the control operation feature having a plurality of control operating options, comprising the following steps: (a) applying a first command to a master control circuit of the memory device; (b) generating a first control signal in said master control circuit in response to said first command; (c) providing an operational code to said memory device, said operational code specifying a desired one of said plurality of control operating options; (d) programming said desired control operating option in response to said first control signal; (e) applying a second command to said master control circuit of the memory device; (f) generating a second control signal in said master control circuit in response to said second command; (g) providing a further operational code specifying a further one of said plurality of control operating options; and (h) programming said control operation feature to have said further one of said plurality of control operating options in response to said second control signal and during an active non-idle state of an array of memory cells of the memory device, such that the array remains simultaneously active in response to an active internal row address signal while the control operation feature is programmed to have the further one of said plurality of control operating options.
Claim 27
Independent Claim
221 words
A method for programming a memory device to have a control operation feature, the control operation feature having a plurality of control operating options, comprising the following steps: (a) applying a first command to a master control circuit of the memory device; (b) generating a first control signal in said master control circuit in response to said first command; (c) providing an operational code to said memory device, said operational code specifying a desired one of said plurality of control operating options; (d) programming said desired control operating option in response to said first control signal; (e) applying a second command to said master control circuit of the memory device; (f) generating a second control signal in said master control circuit in response to said second command; (g) providing a further operational code specifying a further one of said plurality of control operating options; and (h) programming said control operation feature to have said further one of said plurality of control operating options in response to said second control signal and during an active non-idle state of an array of memory cells of the memory device, such that the array remains simultaneously active in response to an active internal row address signal while the control operation feature is programmed to have the further one of said plurality of control operating options.
Claim 28
Independent Claim
209 words
A method for programming a memory device to have a control operation feature, the control operation feature having a plurality of control operating options, comprising the following steps: (a) applying an external set mode register command to a master control circuit of the memory device; (b) generating a first control signal in said master control circuit in response to said external set mode register command; (c) providing an operational code to said memory device, said operational code specifying a desired one of said plurality of control operating options; (d) programming said desired control operating option in response to said first control signal; (e) applying a further command to said master control circuit of the memory device; (f) generating a second control signal in said master control circuit in response to said further command; and (g) programming said control operation feature during an active non-idle state of an array of memory cells of the memory device to have a further one of said plurality of control operating options in response to said second control signal, such that the array remains simultaneously active in response to an active internal row address signal while the control operation feature is programmed to have the further one of said plurality of control operating options.
Claim 29
Independent Claim
209 words
A method for programming a memory device to have a control operation feature, the control operation feature having a plurality of control operating options, comprising the following steps: (a) applying an external set mode register command to a master control circuit of the memory device; (b) generating a first control signal in said master control circuit in response to said external set mode register command; (c) providing an operational code to said memory device, said operational code specifying a desired one of said plurality of control operating options; (d) programming said desired control operating option in response to said first control signal; (e) applying a further command to said master control circuit of the memory device; (f) generating a second control signal in said master control circuit in response to said further command; and (g) programming said control operation feature during an active non-idle state of an array of memory cells of the memory device to have a further one of said plurality of control operating options in response to said second control signal, such that the array remains simultaneously active in response to an active internal row address signal while the control operation feature is programmed to have the further one of said plurality of control operating options.
Claim 30
Independent Claim
209 words
A method for programming a memory device to have a control operation feature, the control operation feature having a plurality of control operating options, comprising the following steps: (a) applying a first command to a master control circuit of the memory device; (b) generating a first control signal in said master control circuit in response to said first command; (c) providing an operational code to said memory device, said operational code specifying a desired one of said plurality of control operating options; (d) programming said desired control operating option in response to said first control signal; (e) applying a column address strobe registration command to said master control circuit of the memory device; (f) generating a second control signal in said master control circuit in response to said column address strobe registration command; and (g) programming said control operation feature during an active non-idle state of an array of memory cells of the memory device to have a further one of said plurality of control operating options in response to said second control signal, such that the array remains simultaneously active in response to an active internal row address signal while the control operation feature is programmed to have the further one of said plurality of control operating options.
Claim 31
Independent Claim
209 words
A method for programming a memory device to have a control operation feature, the control operation feature having a plurality of control operating options, comprising the following steps: (a) applying a first command to a master control circuit of the memory device; (b) generating a first control signal in said master control circuit in response to said first command; (c) providing an operational code to said memory device, said operational code specifying a desired one of said plurality of control operating options; (d) programming said desired control operating option in response to said first control signal; (e) applying a column address strobe registration command to said master control circuit of the memory device; (f) generating a second control signal in said master control circuit in response to said column address strobe registration command; and (g) programming said control operation feature during an active non-idle state of an array of memory cells of the memory device to have a further one of said plurality of control operating options in response to said second control signal, such that the array remains simultaneously active in response to an active internal row address signal while the control operation feature is programmed to have the further one of said plurality of control operating options.
Claim 32
Independent Claim
205 words
A method for programming a memory device to have a control operation feature, the control operation feature having a plurality of control operating options, comprising the following steps: (a) applying a first command to a master control circuit of the memory device; (b) generating a first control signal in said master control circuit in response to said first command; (c) providing an operational code to said memory device, said operational code specifying a desired one of said plurality of control operating options; (d) programming said desired control operating option in response to said first control signal; (e) applying an active row command to said master control circuit of the memory device; (f) generating a second control signal in said master control circuit in response to said active row command; and (g) programming said control operation feature during an active non-idle state of an array of memory cells of the memory device to have a further one of said plurality of control operating options in response to said second control signal, such that the array remains simultaneously active in response to an active internal row address signal while the control operation feature is programmed to have the further one of said plurality of control operating options.
Claim 33
Independent Claim
205 words
A method for programming a memory device to have a control operation feature, the control operation feature having a plurality of control operating options, comprising the following steps: (a) applying a first command to a master control circuit of the memory device; (b) generating a first control signal in said master control circuit in response to said first command; (c) providing an operational code to said memory device, said operational code specifying a desired one of said plurality of control operating options; (d) programming said desired control operating option in response to said first control signal; (e) applying an active row command to said master control circuit of the memory device; (f) generating a second control signal in said master control circuit in response to said active row command; and (g) programming said control operation feature during an active non-idle state of an array of memory cells of the memory device to have a further one of said plurality of control operating options in response to said second control signal, such that the array remains simultaneously active in response to an active internal row address signal while the control operation feature is programmed to have the further one of said plurality of control operating options.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-21 | 2002-03-23 | 2002-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-21 | 2006-03-23 | 2006-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-21 | 2010-03-23 | 2010-09-22 | $7700.00 | Window Closed / Lapsed |